AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 17

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

SERIAL INTERFACE TIMING
All of the internal registers of the AD9898 are accessed through a
3-wire serial interface. The interface consists of a clock (SCK),
serial load (SL), and serial data (SDATA).
The AD9898 has three different register types that are config-
ured by the 3-wire serial interface. They are control registers,
system registers, and mode registers and are described in Table VI.
Register
Control
System
Mode_A
Mode_B
Control Register Serial Interface
The control register 3-wire interface timing requirements are
shown in Figure 7. Control data must be written into the device
one address at a time due to the noncontiguous address spacing
for the control registers. This requires eight bits of address data
followed by 24 bits of configuration data between each active
low period of SL for each address. The SL signal must be kept
high for at least one full SCK cycle between successive writes to
control registers.
REV. 0
Table VI. Type of Serial Interface Registers
SDATA
SCK
Address
0x00 through
0xD6
0x14
0x15
0x16
SL
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
3. THIS TIMING PATTERN MUST BE WRITTEN FOR EACH REGISTER WRITE WITH SL REMAINING HIGH FOR AT
t
DS
LEAST ONE FULL SCK PERIOD BEFORE ASSERTING SL LOW AGAIN FOR THE NEXT REGISTER WRITE.
A7
1
t
LS
A6
No. of Registers
There is a 24-bit register at each
address. Not all addresses are
used. See Table I.
Seventeen 32-bit system registers
at Address 0x14. See Table II.
Eight 32-bit Mode_A registers at
Address 0x15. See Table III.
Eight 32-bit Mode_B registers at
Address 0x16. See Table IV.
t
2
DH
Figure 7. 3-Wire Serial Interface Timing for Control Registers
A5
3
A4
4
A3
5
A2
6
A1
7
–17–
A0
8
System Register Serial Interface
There are seventeen 32-bit system registers that get accessed
sequentially at Address 0x14 beginning with Sys_Reg[0]. When
writing to the system registers, SDATA contains the 8-bit address
of 0x14, followed by Number Writes N[23:0], followed by the
Sys_Reg[31:0] data as shown in Figure 8. The system register
map is listed in Table II.
There are two options available when writing to the system
registers. The choice is automatically determined by the value of
the Number Writes N[23:0] word. If Number Writes N[23:0] =
0x000000, the device gets put into a mode where it expects all
17 Sys_Reg[31:0] data-words to be clocked in before SL is
asserted high. If the Number Writes N[23:0] is decoded as
some number N other than 0x000000, the device expects N
number of registers to be programmed where N is equal to the
value of Number Writes N[23:0]. For example, if Number
Writes N[23:0] = 0x000004, the device would expect data to be
provided for Sys_Reg[3:0]. In all cases, the system registers
would be written to begin with Sys_Reg[0], no matter what the
value of Number Writes N[23:0] is. Note that SL can be brought
high or low during access to system registers, as shown in Figure 8.
Mode_A and Mode_B Register Serial Interface
There are eight 32-bit Mode_A and eight 32-bit Mode_B regis-
ters that get accessed sequentially at Address 0x15 and Address
0x16, respectively. The Mode_A and Mode_B registers get
written to exactly as the system registers are. (See the descrip-
tion above.) The mode registers are listed in Tables III and IV.
Changing operation between Mode_A and Mode_B is done by
setting the 1-bit MODE register (Addr 0x0A). The desired
Mode_A (Addr 0x15) or Mode_B (Addr 0x16) data must be
programmed into the Mode_A or Mode_B registers before
changing the MODE bit.
D23
9
D22
10
D21
11
....
....
D3
29
D2
30
D1
t
31
LH
D0
32
AD9898