AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 35

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

Register
Name
SPAT_EN
SPATLOGIC
V1SPAT_TOG1
V1SPAT_TOG2
V2SPAT_TOG1
V2SPAT_TOG2
V3SPAT_TOG1
V3SPAT_TOG2
V4SPAT_TOG1
V4SPAT_TOG2
Special Vertical Timing (SPAT)
The AD9898 provides additional special vertical timing (SPAT)
generation, which is output in the same line as the VSG pulse.
The SPAT timing allows for configuring a second vertical out-
put pulse in the VSG line. Tables XIX and XX list the registers
used to generate the SPAT timing.
Figures 35 and 36 show how the SPAT timing can be either an
AND case or an OR case, depending on the value set in the
SPATLOGIC register. As these figures show, the internal SPAT
timing for the AND case will start High and then go Low at the
first VxSPAT_TOG1 position. In the OR case, the internal
REV. 0
TIMING FOR V2 WITH
V2 OUTPUT WITH
INTERNAL SPAT
SPATLOGIC = 1
Bit
Width
1
4
13
13
13
13
13
13
13
13
SPAT APPLIED
SPAT APPLIED
ST COUNTER
INTERNAL V2
WITHOUT
(FIXED)
13-BIT
VSGx
HD
VD
Figure 35. SPAT Example Applied to V2 with SPATLOGIC = xx1x
Register Type
Control (Addr 0x0A)
Control (Addr 0x0A)
Mode_Reg(5)
Mode_Reg(5)
Mode_Reg(6)
Mode_Reg(6)
Mode_Reg(6 and 7)
Mode_Reg(7)
Mode_Reg(7)
Mode_Reg(7 and 8)
1. THE VxSPAT_TOG1 AND VxSPAT_TOG2 REGISTERS REFERENCE THE 13-BIT ST COUNTER.
2. THE INTERNAL SPAT TIMING IS APPLIED IN THE SAME LINE AS THE VSGx PULSE.
PROGRAMMABLE CLOCK POSITIONS
1. VxSPAT_TOG1 (PROGRAMMABLE AT MODE_REGs).
2. VxSPAT_TOG2 (PROGRAMMABLE AT MODE_REGs).
Table XIX. HD and VD Registers
Reference
ST
ST
ST
ST
ST
ST
ST
ST
Counter
–35–
SPAT timing will initially start Low and then toggle High at the
first VxSPAT_TOG1 position. This provides the ability to
output the second vertical pulse when the internal Vx pulse is
in both High and Low states.
Range
Pixels
0–8192
0–8192
0–8192
0–8192
0–8192
0–8192
0–8192
0–8192
SPATLOGIC [3:0]
3
V4
Table XX. SPATLOGIC Register (Addr 0x0A)
2
V3
1
SPAT Enable Control
SPAT Logic Setting
Polarity Change Position Start for V1 SPAT
Polarity Change Position End for V1 SPAT
Polarity Change Position Start for V2 SPAT
Polarity Change Position End for V2 SPAT
Polarity Change Position Start for V3 SPAT
Polarity Change Position End for V3 SPAT
Polarity Change Position Start for V4 SPAT
Polarity Change Position End for V4 SPAT
Description
(0 = SPAT Disabled, 1 = SPAT Enabled)
1
V2
2
0
V1
Description
0 = OR, 1 = AND
AD9898