AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 15

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

Register
Mode_Reg(0) (31:24)
Mode_Reg(1) (31:21)
Mode_Reg(2) 31
Mode_Reg(3) (31:27)
Mode_Reg(4) (31:29)
Mode_Reg(5) (31:19)
Mode_Reg(6) (31:25)
Mode_Reg(7) 31
Mode_Reg(8) (31:24)
*Register value must be a gray code number. (See Gray Code Registers section.)
REV. 0
Content
(23:0)
(20:9)
8
7
(6:0)
(30:28)
(27:25)
(24:22)
(21:19)
(18:16)
15
14
13
12
11
(10:3)
(2:0)
(26:19)
(18:11)
(10:9)
(8:7)
(6:5)
(4:3)
(2:0)
(28:26)
(25:23)
(22:12)
(11:1)
0
(18:6)
(5:0)
(24:12)
(11:0)
(30:18)
(17:5)
(4:0)
(23:11)
(10:9)
(8:0)
Bit
Width (Decimal) Register Name
8
24
11
12
1
1
7
1
3
3
3
3
3
1
1
1
1
1
8
3
5
8
8
2
2
2
2
3
3
3
3
11
11
1
13
13
6
7
13
12
1
13
13
5
8
13
2
9
Default
NA
262
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
988
1138
1078
1168
958
1138
988
1228
1392
3
NA
1139
1
0
1
0
0
0
0
Table IV. Mode_B Register Map (Addr 0x16)
SCP2
VTPREP1
V1SPAT_TOG1
V2SPAT_TOG1
V4SPAT_TOG2
Mode_B_Addr
Mode_B_Number_N Number N Register Writes (0x000000 = Write All Registers)
VDLEN
HDLASTLEN*
VSGSEL0
VSGSEL1
VSGACTLINE
SUBCKSEL
VTPSEQPTR0
VTPSEQPTR1
VTPSEQPTR2
VTPSEQPTR3
VTPSEQPTR4
CLPEN0
CLPEN1
CLPEN2
CLPEN3
CLPEN4
SCP1
SCP2
SCP3
SCP4
VTPSEL0
VTPSEL1
VTPSEL2
VTPSEL3
VTPREP0
VTPREP2
VTPREP3
SVREP0
SVREP3
V1SPAT_TOG2
V2SPAT_TOG1
V2SPAT_TOG2
V3SPAT_TOG1
V3SPAT_TOG1
V3SPAT_TOG2
V4SPAT_TOG1
V4SPAT_TOG2
SECONDVPOS
VPATSECOND
–15–
Register Description
Mode_B Address Is (Addr 0x16)
VD Counter Value
Number of Pixels in Last Line (Gray Code Number)
VSG1 Sequence Selector (See Table XXIII)
VSG2 Sequence Selector (See Table XXIII)
VSG Active Line
Select One of Two SUBCK Patterns
Vertical Transfer Sequence Region No. 0
Vertical Transfer Sequence Region No. 1
Vertical Transfer Sequence Region No. 2
Vertical Transfer Sequence Region No. 3
Vertical Transfer Sequence Region No. 4
CLPOB Output Control No. 1
CLPOB Output Control No. 2
CLPOB Output Control No. 3
CLPOB Output Control No. 4
CLPOB Output Control No. 5
Sequence Change Position No. 1
Sequence Change Position No. 2
Sequence Change Position No. 3
Sequence Change Position No. 4
Vertical Pattern Selection 0
Vertical Pattern Selection 1
Vertical Pattern Selection 2
Vertical Pattern Selection 3
Number of VTP0 Pulse Repetitions for Pattern0
Number of VTP1 Pulse Repetitions for Pattern1
Number of VTP2 Pulse Repetitions for Pattern2
Number of VTP0 Pulse Repetitions for Pattern3
Vertical Sweep Repetition Number for CCD Region0
Vertical Sweep Repetition Number for CCD Region3
Unused
Polarity Change Position Start for V1 SPAT
Polarity Change Position End for V1 SPAT
Polarity Change Position Start for V2 SPAT
Polarity Change Position End for V2 SPAT
Polarity Change Position Start for V3 SPAT
Polarity Change Position End for V3 SPAT
Polarity Change Position Start for V4 SPAT
Polarity Change Position End for V4 SPAT
Second V Pattern Output Position
Selected Second V Pattern Group for VSG Active Line
Unused
AD9898