AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 10

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9898
Address
00
01
02
03
04
05
Content
(23:0)
(23:21)
20
(19:18)
17
16
(15:14)
13
12
(11:10)
(9:8)
7
6
5
4
(3:1)
0
(23:22)
(21:16)
(15:14)
(13:8)
(7:6)
(5:0)
(23:17)
16
(15:14)
(13:8)
(7:6)
(5:0)
(23:22)
(21:16)
(14:12)
11
(10:8)
(7:3)
(2:0)
(23:10)
9
8
(7:2)
1
0
Bit
Width
23
3
1
2
1
1
2
1
1
2
2
1
1
1
1
3
1
2
6
2
6
2
6
7
1
2
6
2
6
2
6
3
1
3
5
3
14
1
1
6
1
1
Table I. Control Register Address Map (Register Names Are Subject to Change)
Default
Value
000000
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0x34
0
0x18
0
0x0B
0x00
0
0
0x00
0
0x10
0
0x20
5
0
5
0x00
2
0x0000
0
0
00
0
1
Name
SW_RESET
MSHUTPAT
SHDLOC
DCLKPHASE
DOUTPHASE
RGNEGLOC
REFBLACK
H2DRV
RGDRV
Register
HBLKMASK
SYNCPOL
SUBCKMODE_HP
SUBCKSUPPRESS
MSHUT/VGATE_EN
MSHUT/SUBCK_EN
CLP_CONT
CLP_MODE
VDMODE
SHPLOC
H1BLKRETIME
H1POSLOC
H1DRV
AFESTBY
DIGSTBY
OUTCONT_REG
OUTCONT_ENB
–10–
Register Description
Software Reset = 000000. (Reset all registers to default.)
Unused
Unused. Test Mode. Should be set = 0.
Unused
Masking Polarity for H1 during blanking period (0 = Low, 1 = High)
External SYNC Active Polarity (0 = Active Low)
Unused
High Precision Shutter Mode Operation (0 = Single Pulse, 1 = Multiple
Pulse)
Suppress First SUBCK after Last VSG Line Pulse (0 = No Suppression,
1 = Suppression of 1 SUBCK)
Unused
Selects MSHUT Pattern (See Figure 44) (0 = MSHUTPAT0,
1 = MSHUTPAT1, 2 = MSHUTPAT2, 3 = MSHUTPAT3)
MSHUT Masking of VGATE Input (0 = MSHUT does not mask
VGATE, 1 = MSHUT does mask VGATE)
MSHUT Masking of SUBCK (0 = MSHUT does not mask SUBCK,
1 = MSHUT does mask SUBCK)
CLPOB Control (0 = CLPOB OFF, 1 = CLPOB ON)
CLPOB CCD Region Control (See Table XII)
Unused
VD Synchronous/Asynchronous Mode Setting (0 = VD Synchronous,
1 = VD Asynchronous)
Unused
SHD Sample Location
Unused
SHP Sample Location
DCLK Pulse Adjustment
Data Output [9:0] Phase Adjustment
Unused
Retimes the H1 HBLK to Internal Clock
Unused
H1 Positive Edge Location
Unused
RG Negative Edge Location
Unused
Black Clamp Level
H2 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA)
Unused
H1 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA)
Unused
RG Drive Strength (0 = Off, 1 = 2.15 mA, 2 = 4.2 mA, 3 = 6.45 mA,
4 = 8.6 mA, 5 = 10.75 mA, 6 = 12.9 mA, 7 = 15.05 mA)
Unused
AFE Standby (0 = Standby , 1 = Normal Operation)
Digital Standby (0 = Standby , 1 = Normal Operation)
Unused
Internal OUTCONT Signal Control (0 = Digital Outputs held at fixed
dc level, 1 = Normal Operation)
External OUTCONT Signal Input Pin 43 Control (0 = Pin Enabled,
1 = Pin Disabled)
REV. 0