AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 34

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9898
Special Vertical Sweep Mode Operation
The AD9898 contains a special mode of vertical timing operation
called sweep mode. This mode is used to generate a continu-
ous number of repetitive vertical pulses that span multiple HD
lines. One example of when this mode may be needed is the
start of the CCD readout operation. At the end of the image
exposure, but before the image is transferred by the sensor gate
pulses, the vertical interline CCD registers should be cleared of
all charge. The charge can be shifted out quickly with a long
series of pulses on the V1–V4 outputs. This operation will span
multiple HD line lengths.
Figure 31. NonOverlapping Example for Normal Vertical Timing Operation with SVREP_MODE = 0 and VTPREPx = 4
Figure 32. Overlapping Example for Normal Vertical Timing Operation with SVREP_MODE = 0 and VTPREPx = 8
SVREP_MODE
0
0
1
1
V1–V4
V1–V4
V1–V4
V1–V4
HD
HD
HD
HD
Figure 33. Sweep Mode Timing Example with SVREP_MODE = 1 and SVREP0 = 28
Figure 34. Sweep Mode Timing Example with SVREP_MODE = 2 and SVREP3 = 28
0
1
0
1
SCP0
SCP3
0
0
Description of Sweep Mode Operation
Normal Vertical Timing Operation in All CCD Regions
Special Vertical Sweep Mode Timing Output in CCD Region0 Only
Special Vertical Sweep Mode Timing Output in CCD Region3 Only
Special Vertical Sweep Mode Timing Output in CCD Region0 and CCD Region3
Table XVIII. Description of SVREP_MODE Register
1
1
NOT OUTPUT BECAUSE THE 8TH
REPETITION OVERLAPS WITH HD
CCD REGION0
CCD REGION3
–34–
Normally the sequences are contained within one HD line length,
but with the sweep mode enabled, the HD boundaries will be
ignored until the region is finished. The special vertical sweep
mode operation is only output in CCD Region0 and CCD
Region3. (See Figures 33 and 34.) The SVREP_MODE register
located at control Address 0x0A is used to enable and configure
the special sweep mode operation as described in Table XVIII.
The maximum number of repeats in each region is 2048
while operating in this mode using the SVREP0 and SVREP3
Mode_Reg(4) registers.
2
2
SCP1 = 3
SCP4 = 3
0
0
REV. 0