AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 25

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

Register
Name
CLP_CONT 1
CLP_MODE 1
CLPTOG1
CLPTOG2
CLPEN0
CLPEN1
CLPEN2
CLPEN3
CLPEN4
HORIZONTAL CLAMPING AND BLANKING
The AD9898’s horizontal clamping and blanking pulses are
programmable to suit a variety of applications. Similar to verti-
cal timing generation, individual sequences are defined for each
signal and are then organized into multiple regions during
image readout. This allows the dark pixel clamping and blanking
patterns to be changed at each stage of the readout to accommo-
date different image transfer timing and high speed line shifts.
Controlling CLPOB Clamp Pulse Timing
The AFE horizontal CLPOB pulse is generated based on the
12-bit gray code counter. Once the length of the 12-bit gray
code counter is set using the HDLEN register (Sys_Reg(12)),
CLPTOG1 and CLPTOG2 registers (Sys_Reg(15 and16)) can
be used to place the CLPOB pulse location, as shown in Figure 19.
Table XII lists all CLPOB registers that are used to configure
and control the placement and output of the CLPOB pulse.
The length of the last HD line is set using the HDLASTLEN
register (Sys_Reg(1)). Figure 20 shows that no CLPOB pulse
will be asserted when the last HD length set by HDLASTLEN
is shorter than the regular HD length set by HDLEN.
REV. 0
GRAY COUNTER
+ SETUP
CLPOB
12-BIT
Bit
Width Register Type
12
12
1
1
1
1
1
VD
HD
PROGRAMMABLE CLOCK POSITIONS
1. CLPTOG1 (SYS_REG(15))
2. CLPTOG2 (SYS_REG(15 AND 16))
Control (0x01)
Control(0x01)
Sys_Reg(15)
Sys_Reg(15 and 16) HD
Mode_Reg(2)
Mode_Reg(2)
Mode_Reg(2)
Mode_Reg(2)
Mode_Reg(2)
Figure 19. Location of CLPOB Using CLPTOG1 and CLPTOG2 Registers
Reference
Counter
HD
Table XII. CLPOB Registers
Range
0–4095 Pixel Locations CLPOB Toggle Position 1 (Gray Code Number)
0–4095 Pixel Locations CLPOB Toggle Position 2 (Gray Code Number)
–25–
Figure 21 shows that no CLPOB pulse will be applied when the
last HD length set by HDLASTLEN is longer than the regular
HD length. Note that the CLPOB pulse is applied in the last
line only when HDLASTLEN = HDLEN.
CLPOB
CLPOB
HD
HD
Figure 20. Last HD Shorter Than Regular HD
Figure 21. Last HD Longer Than Regular HD
CLPOB CCD Region Control
CLPOB Control for CCD Region 0
CLPOB Control for CCD Region 1
CLPOB Control for CCD Region 2
CLPOB Control for CCD Region 3
CLPOB Control for CCD Region 4
Description
CLPOB Control (0 = CLPOB Off, 1 = CLPOB On)
(0 = Enable CLPENx Register Settings,
1 = Disable CLPENx Register Settings)
(0 = CLPOB Disabled, 1 = CLPOB Enabled)
(0 = CLPOB Disabled, 1 = CLPOB Enabled)
(0 = CLPOB Disabled, 1 = CLPOB Enabled)
(0 = CLPOB Disabled, 1 = CLPOB Enabled)
(0 = CLPOB Disabled, 1 = CLPOB Enabled)
1
LAST LINE
LAST LINE
2
AD9898