AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 20

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

AD9898
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9898
features on-chip output drivers for the RG and H1–H2 outputs.
They are sufficiently powerful to directly drive the CCD inputs.
The H-driver current can be adjusted for optimum rise/fall time
into a particular load by using the H1DRV and H2DRV regis-
ters (Addr 0x04). The RG drive current is adjustable using the
RGDRV register (Addr 0x04). The H1DRV and H2DRV regis-
ter is adjustable in 4.3 mA increments. The RGDRV register is
adjustable in 2.15 mA increments. All DRV registers have a setting
of 0 equal to OFF or three-state, and the maximum setting of 7.
POSITION
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (
PERIOD
1 PIXEL
CLI
(INTERNAL)
SIGNAL
t
CLIDLY
CCD
cds
RG
H1
H2
1
5
PROGRAMMABLE CLOCK POSITIONS
1. RG RISING EDGE (FIXED EDGE AT 000000).
2. RG FALLING EDGE (RGNEGLOC (ADDR 0x03)).
3. SHP SAMPLE LOCATION (SHPLOC (ADDR 0x02)).
4. SHD SAMPLE LOCATION (SHDLOC (ADDR 0x02)).
5. H1 RISING EDGE LOCATION (H1POSLOC (ADDR 0x03))
6. H1 NEGATIVE EDGE LOCATION (FIXED AT (H1POSLOC + 24 STEPS)).
7. H2 IS ALWAYS THE INVERSE OF H1.
Figure 11. High Speed Clock Resolution from CLI Master Clock Input
P[0]
2
Figure 12. High Speed Clock Programmable Locations
3
6
P[12]
4
–20–
As shown in Figure 13, the H2 output is the inverse of H1. The
internal propagation delay resulting from the signal inversion is
less than 1 ns, which is significantly less than the typical rise
time driving the CCD load. This results in an H1/H2 crossover
voltage of approximately 50% of the output swing. The cross-
over voltage is not programmable.
Digital Data Outputs
The AD9898 DOUT[9:0] and DCLK phases are independently
programmable using the DOUTPHASE register (Addr 0x02)
and DCLKPHASE register (Addr 0x02) (see Figure 15).
P[24]
t
CLIDLY
P[36]
= 6 ns TYP).
P[48] = P[0]
REV. 0