AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 45

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

VARIABLE GAIN AMPLIFIER
The VGA provides a gain range of 6 dB to 40 dB, programmable
with 10-bit resolution through the serial digital interface. The
minimum gain of 6 dB is needed to match a 1 V input signal
with the ADC full-scale range of 2 V.
The VGA gain curve follows a linear-in-dB characteristic. The
exact VGA gain can be calculated for any gain register value
using the equation
where the code range is 0 to 1023. Figure 50 shows a typical
AD9898 VGA gain curve.
REV. 0
42
36
30
24
18
12
6
0
127
Figure 50. VGA Gain Curve
Gain
255
I/O
DCLK1
DCLK2
VD
HD
RG
H1
H2
V1
V2
V3
V4
SUBCK
VSG1
VSG2
STROBE
MSHUT
FD
NOTES
1
2
OUTCONT_REG is a register setting located at Addr 0x05. It defaults to 0 at power-up.
VD and HD operating in master mode.
VGA GAIN REGISTER CODE
=
(
2
2
0 035
383
.
511
×
Code
OCONT_REG
ACTIVE
ACTIVE
H
H
L
H
L
H
H
H
H
H
H
H
L
L
H
639
)
+
5 3
.
767
895
1
= 0
Table XXVI. I/O Levels
1023
SW_RESET
ACTIVE
ACTIVE
H
H
L
H
L
L
L
L
H
H
L
H
L
L
L
–45–
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference, selected by the user in the clamp level
register. Any value between 0 LSB and 63 LSB may be pro-
grammed with 6-bit resolution. The resulting error signal is
filtered to reduce noise, and the correction value is applied to
the ADC input through a D/A converter. Normally the optical
black clamp loop is turned on once per horizontal line, but this
loop can be updated more slowly to suit a particular application.
The optical black clamp is controlled by the CLPOB signal,
which is fully programmable (see Horizontal Clamping and
Blanking section). System timing examples are shown in the
Horizontal Timing Sequence Example section. The CLPOB
pulse should be placed during the CCD’s optical black pixel.
It is recommended that the CLPOB pulse duration be at least
20 pixels wide. Shorter pulsewidths may be used, but the ability
to track low frequency variations in the black level will be reduced.
A/D Converter
The AD9898 uses a high performance 10-bit ADC architecture,
optimized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.5 LSB. The ADC
uses a 2 V input range. Better noise performance results from
using a larger ADC full-scale range.
Digital I/O States for Different Operating Conditions
Table XXVI describes the state of the digital I/Os for different
operating conditions.
DIGSTBY
L
L
H
H
L
H
L
H
L
L
H
H
H
H
L
L
L
SYNC
ACTIVE
ACTIVE
H
H
ACTIVE
ACTIVE
ACTIVE
FREEZE
FREEZE
FREEZE
FREEZE
FREEZE
FREEZE
FREEZE
FREEZE
FREEZE
FREEZE
AD9898