AD9898KCP-20 Analog Devices Inc, AD9898KCP-20 Datasheet - Page 11

• Manufacturer Part Number: AD9898KCP-20
• Description: IC CCD SIGNAL PROC/GEN 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9898KCP-20

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LFCSP EP
• Number Of Channels: 3
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

Address
0A
(VD
SyncReg)* 9
0B
(VD
SyncReg)* 16
0C
(VD
SyncReg)* 16
0D
(VD
SyncReg)* (10:0)
0E
(VD
SyncReg)* 16
D5
D6
*This register defaults to VD synchronous mode type at power up. VD sync type registers do not get updated until the first falling edge of VD is asserted after the
REV. 0
register has been programmed. VD sync type registers can be programmed to be asynchronous registers by setting VDMODE = 1 (Addr 0x01).
Content
23
22
(21:16)
(15:12)
(11:10)
8
(7:4)
(3:2)
1
0
(23:22)
21
20
(19:17)
15
(14:12)
11
(10:0)
(23:21)
20
(19:18)
17
15
(14:12)
11
(10:0)
(23:17)
16
(15:11)
(23:21)
20
(19:18)
17
(15:10)
(9:0)
(23:4)
3
2
(1:0)
(23:1)
0
Bit
Width
1
1
6
4
2
1
1
4
2
1
1
2
1
1
3
1
1
3
1
11
3
1
2
1
1
1
3
1
11
7
1
5
11
3
1
2
1
1
6
10
20
1
1
2
23
1
Table I. Control Register Address Map (Register Names Are Subject to Change)
Default
Value
0
0
0x00
0
0
0
0
C
3
0
0
0
1
1
0
0
0
0
0
0x7FF
0
0
0
0
0
0
0
0
0x000
0
0x000
0
0
0
0
0
0x00
0x000
0x00000
1
0
0
0x000000
1
Register
Name
FDPOL
VSGMASK
SYNCCNT
SVREP_MODE
HBLKEXT
HPULSECNT
SPATLOGIC
SVOS
SPAT_EN
MODE
SUBCK_EN
VSG_EN
STROBE_EN
SUBCKNUM_HP
SUBCKNUM
MSHUTINIT
MSHUTEN
MSHUTPOS_HP
MSHUTPOS
VSUBPOL
VSUBTOG
VGAGAIN
DCLK2SEL
DCLK1SEL
CLKDIV
SLAVE_MODE
–11–
Register Description
Unused
FD Polarity Control (0 = Low, 1 = High)
VSG Masking (See Table XXIII)
External SYNC Setting
Super Vertical Repetition Mode
H Pulse Blanking Extend Control
H Pulse Control during Blanking
SPAT Logic Setting (See Table XX)
Second V Output Setting (10 = Output Repetition 1)
SPAT Control (0 = SPAT Disable, 1 = SPAT Enable)
Mode Control Bit (0 = Mode_A, 1 = Mode_B)
Unused
SUBCK Output Enable Control (0 = Disable, 1 = Enable)
VSG Output Enable Control (0 = Disable, 1 = Enable)
Unused
STROBE Output Control (0 = STROBE Output Held Low,
1 = STROBE Output Enabled)
Unused
High Precision Shutter SUBCLK Pulse Position/Number
Unused
Total Number of SUBCKs per Field
Unused
MSHUT Initialize (1 = Forces MSHUT Low)
Unused
Unused
MSHUT Control ( 0 = MSHUT Held at Last State, 1 = MSHUT Output)
Unused
MSHUT Position during High Precision Operation
Unused
MSHUT Position during Normal Operation
Unused
VSUB Active Polarity (0 = Low, 1 = High)
Unused
VSUB Toggle Position. Active starting line in any field.
Unused
Unused. Test Mode. Should be set = 0.
Unused
Unused. Test Mode. Should be set = 0.
Unused. Test Mode. Should be set = 0.
Unused
VGA Gain
Unused
DCLK2 Selector (0 = Select Internal FD Signal to be Output on FD/
DCLK2 Pin 16, 1 = Select CLI to be Output on FD/DCLK2 Pin 16)
DCLK1 Selector (0 = Select DLL Version for DCLK1 Output,
1 = Select CLI for DCLK1 Output)
Input Clock Divider (0 = No Division, 1 = 1/2, 2 = 1/3, 3 = 1/4)
Unused
Operating Mode ( 0 = Master Mode, 1 = Slave Mode)
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