AD9882AKSTZ-100 Analog Devices Inc, AD9882AKSTZ-100 Datasheet
AD9882AKSTZ-100
Specifications of AD9882AKSTZ-100
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AD9882AKSTZ-100 Summary of contents
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FEATURES Analog interface 140 MSPS maximum conversion rate Programmable analog bandwidth 0 1.0 V analog input range 500 ps p-p PLL clock jitter at 140 MSPS 3.3 V power supply Full sync processing Midscale clamping 4:2:2 output format ...
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AD9882A TABLE OF CONTENTS Specifications............................................................................................3 Absolute Maximum Ratings ..................................................................6 Explanation of Test Levels..................................................................6 ESD Caution ........................................................................................6 Pin Configuration and Function Descriptions....................................7 Pin Descriptions of Shared Pins between Analog and Digital Interfaces ..............................................................................................8 Serial Port (2-Wire) ............................................................................8 Data Outputs........................................................................................8 Pin Function ...
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... Input Current, High (I ) Full IH Input Current, Low (I ) Full IL Input Capacitance 25°C DIGITAL OUTPUTS 1 Output Voltage, High (V ) Full OH Output Voltage, Low (V ) Full OL Duty Cycle, DATACK Full AD9882AKSTZ-100 Test Level Min Typ Max 8 I ±0.5 +1.25/–1.0 VI +1.35/–1.0 I ±0.5 ±1.85 VI ±2.0 VI Guaranteed VI 0.5 VI 1.0 ...
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... OUT OH Output Low Drive (I )( OLD OUT OL DATACK High Drive (V )( OHC OUT OH DATACK Low Drive (V )( OLC OUT OL Differential Input Voltage Single-Ended Amplitude AD9882AKSTZ-100 Test Level Min Typ Max Binary IV 3.15 3.3 3.45 IV 2.2 3.3 3.45 IV 3.15 3.3 3.45 V 162 228 237 VI 30 ...
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... L Output drive = high Output drive = medium Output drive = low Output drive = high Output drive = medium Output drive = low Rev Page AD9882AKSTZ Temp Test Level Min Typ Max Full IV 3.15 3.3 3.45 Full IV 2.2 3.3 3.45 Full IV 3.15 3.3 3.45 25°C V 237 25° ...
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AD9882A ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Analog Inputs V REF Digital Inputs Digital Output Current Operating Temperature Storage Temperature Maximum Junction Temperature Maximum Case Temperature Stresses above those listed under Absolute Maximum Ratings may cause ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 GREEN<7> 2 GREEN<6> 3 GREEN<5> 4 GREEN<4> 5 GREEN<3> 6 GREEN<2> 7 GREEN<1> 8 GREEN<0> GND 11 BLUE<7> 12 BLUE<6> 13 BLUE<5> 14 BLUE<4> 15 BLUE<3> 16 BLUE<2> 17 ...
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AD9882A Pin Type Mnemonic Data Outputs RED [7:0] GREEN [7:0] BLUE [7:0] Data Clock Output DATACK Digital Video Data R X0+ Inputs R X0– R X1+ R X1– R X2+ R X2– Digital Video Clock R XC+ Inputs R XC– ...
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Table 5. Analog Interface Pin List Pin Type Analog Video Inputs External Sync/Clock Sync Outputs Voltage Reference Clamp Voltages PLL Filter Power Supply PIN FUNCTION DETAIL: ANALOG INTERFACE Inputs R —Analog Input for Red Channel AIN G —Analog Input for ...
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AD9882A FILT—External Filter Connection For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter as shown in Figure 8 to this pin. For optimal performance, minimize noise and parasitics on this node. REFBYPASS—Internal Reference Bypass ...
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Table 6. Interface Selection Controls AIO Analog Interface Digital Interface (0xF Bit 2) Detect Detect Table 7. Power-Down Modes, 4:2:2 and 4:4:4 Format Descriptions Analog Power- Interface 1 ...
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AD9882A THEORY OF OPERATION: INTERFACE DETECTION ACTIVE INTERFACE DETECTION AND SELECTION The AD9882A includes circuitry to detect whether an interface is active or not (see Table 6). For detecting the analog interface, the circuitry monitors the presence of Hsync, Vsync, ...
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THEORY OF OPERATION AND DESIGN GUIDE: ANALOG INTERFACE GENERAL DESCRIPTION The AD9882A is a fully integrated solution for capturing analog RGB signals and digitizing them for display on flat panel moni- tors or projectors. The device is ideal for implementing ...
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AD9882A An offset is then introduced, which results in the ADC producing a black output (Code 0x00) when the known black input is present. The offset then remains in place when other signal levels are processed, and the entire signal ...
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SYNC-ON-GREEN (SOG) The sync-on-green input operates in two steps. First, it sets a baseline clamp level off of the incoming video signal with a negative peak detector. Second, it sets the sync trigger level (nominally 150 mV above the negative ...
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AD9882A Four programmable registers are provided to optimize the performance of the PLL. These registers are 1. The 12-bit divisor register (Registers 0x01 and 0x02). The input Hsync frequencies range from 15 kHz to 110 kHz. The PLL multiplies the ...
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TIMING: ANALOG INTERFACE The following timing diagrams show the operation of the AD9882A. The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally. ...
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AD9882A TIMING DIAGRAMS RGBIN HSYNC PXCK HS 5-PIPE DELAY ADCCK DATACK DATAOUT HSOUT RGBIN HSYNC PXCK HS 5-PIPE DELAY ADCCK DATACK GOUTA ROUTA HSOUT ...
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THEORY OF OPERATION: DIGITAL INTERFACE Table 11. Digital Interface Pin List Pin Type Mnemonic Digital Video Data R X0+ Inputs R X0– R X1+ R X1– R X2+ R X2– Digital Video Clock R XC+ Inputs R XC– Termination Control ...
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AD9882A MCL—HDCP Master Serial Port Data Clock Connects to the EEPROM for reading the encrypted HDCP keys. MDA—HDCP Master Serial Port Data I/O Connects to the EEPROM for reading the encrypted HDCP keys. CTL—Digital Control Outputs These pins output the ...
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HDCP keys as required by the HDCP v. 1.0 specification. The AD9882A includes hardware for decrypting the keys in the external EEPROM. ADI provides a royalty-free license for the proprietary software needed by customers to encrypt ...
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AD9882A GENERAL TIMING DIAGRAMS: DIGITAL INTERFACE Rx0 DIFF Rx1 t CCS DIFF Rx2 Figure 13. Digital Output Rise and Fall Times CIP CIP CIH CIH T Figure 14. ...
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SERIAL REGISTER MAP The AD9882A is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 12. ...
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AD9882A Read and Hexadecimal Write or Default Address Read Only Bit Value 4 ***0 **** 3 **** 0*** 2 **** *0** 1 **** **0* 0 **** ***0 0x11 R/W 7 0*** **** 6 *0** **** 5 **0* **** 4 ***0 ...
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Read and Hexadecimal Write or Default Address Read Only Bit Value 0x16 0x17 R/W 7–0 0000 0000 0x18 R/W 7–0 0000 000X 0x19 R/W 7–0 0000 010X 0x1A R/W 7–0 0011 1111 0x1B ...
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AD9882A 2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP IDENTIFICATION 0x00 7–0 Chip Revision An 8-bit register that represents the silicon revision. PLL DIVIDER CONTROL 0x01 7–0 PLL Divide Ratio MSBs The eight most significant bits of the 12-bit PLL divide ratio ...
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CLAMP TIMING 0x05 7–0 Clamp Placement An 8-bit register that sets the position of the internally generated clamp. When clamp function (Register 0x11, Bit clamp signal is generated internally at a position established by the clamp ...
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AD9882A 0x0F 1 AIS Active Interface Select This bit is used under two conditions used to select the active interface when the override bit is set (Register 0x0F, Bit 2). Alternatively used to determine the active ...
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Table 23. Active Vsync Override Settings Override Result 0 Autodetermines the active Vsync 1 Override; Bit 0 determines the active Vsync. The default for this register is 0. 0x10 0 Active Vsync Select This bit is used to select the ...
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AD9882A 0x11 1 Coast Input Polarity This bit indicates the polarity of the coast signal that is applied to the PLL coast input. This register can be used only when coast is disabled and Register 0x11, Bit 2 is set ...
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Output Mode Select This bit configures the output data in 4:2:2 mode. This mode can be used to reduce the number of data lines used from for applications using YPbPr graphics signals. A timing ...
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AD9882A Table 45. Active Hsync Results Hsync Detect SOG Detect Override Register Register Register 0x15,Bit 7 0x,10 Bit 4 0x,15 Bit AHS = 0 ...
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SCL is low. If SDA changes state while SCL is high, the serial interface interprets that action as a start or stop sequence. The five components to serial bus operation are • Start signal • Slave address ...
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AD9882A Serial Interface Read/Write Examples Example 1. Write to one control register • Start signal • Slave address byte (R/ W bit = LOW) • Base address byte • Data byte to base address • Stop signal Example 2. Write ...
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SYNC PROCESSING ENGINE SYNC SLICER This section describes the basic operation of the sync processing engine (see Figure 20). The purpose of the sync slicer is to extract the sync signal from the green graphics channel. A sync signal is ...
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AD9882A PCB LAYOUT RECOMMENDATIONS The AD9882A is a high precision, high speed analog device. To derive the maximum performance from the part important to have a well laid out board. The following is a guide for designing a ...
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PLL Place the PLL loop filter components as close to the FILT pin as possible. Do not place any digital or other high frequency traces near these components. Use the values suggested in the data sheet with 10% or smaller ...
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... AD9882A OUTLINE DIMENSIONS 10° 6° 1.45 2° 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model 1 AD9882AKSTZ-100 1 AD9882AKSTZ-140 AD9882A/PCB Pb-free part. 1.60 MAX 100 0.75 12° 1 TYP 0.60 0.45 PIN 1 SEATING PLANE 0.20 0.09 VIEW A 7° ...
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NOTES Rev Page AD9882A ...
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AD9882A NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the 2 purchaser under the Philips I C Patent Rights to use these components ...