AD9882AKSTZ-100 Analog Devices Inc, AD9882AKSTZ-100 Datasheet - Page 15

• Manufacturer Part Number: AD9882AKSTZ-100
• Description: IC INTERFACE/DVI 100MHZ 100LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9882AKSTZ-100

• Applications: Video
• Interface: Analog, DVI
• Voltage - Supply: 3.15 V ~ 3.45 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Supply Voltage Range: 3.15V To 3.45V, 2.2V To 3.45V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Msl: MSL 3 - 168 Hours
• Update Rate: 140MSPS
• Bandwidth: 300MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SYNC-ON-GREEN (SOG)
The sync-on-green input operates in two steps. First, it sets a
baseline clamp level off of the incoming video signal with a
negative peak detector. Second, it sets the sync trigger level
(nominally 150 mV above the negative peak). The exact trigger
level is variable and can be programmed via Register 0x0F,
Bits 7 to 3. The sync-on-green input must be ac-coupled to the
green analog input through its own capacitor as shown in
Figure 5. The value of the capacitor must be 1 nF ±20%. If sync-
on-green is not used, this connection is not required and
SOGIN should be left unconnected. Note that the sync-on-
green signal is always negative polarity. See the Sync Processing
Engine section for further information.
CLOCK GENERATION
A phase-locked loop (PLL) is employed to generate the pixel
clock. The Hsync input provides a reference frequency for the
PLL. A voltage controlled oscillator (VCO) generates a much
higher pixel clock frequency. This pixel clock is divided by the
PLL divide value (Registers 0x01 and 0x02) and phase com-
pared with the Hsync input. Any error is used to shift the VCO
frequency and maintain lock between the two signals.
The stability of this clock is a very important element in provid-
ing the clearest and most stable image. During each pixel time,
there is a period during which the signal is slewing from the old
pixel amplitude and settling at its new value. Then there is a
time when the input voltage is stable, before the signal must
slew to a new value (Figure 6). The ratio of the slewing time to
the stable time is a function of the bandwidth of the graphics
DAC and the bandwidth of the transmission system (cable and
termination). It is also a function of the overall pixel rate.
Clearly, if the dynamic characteristics of the system remain
fixed, then the slewing and settling time is likewise fixed. This
time must be subtracted from the total pixel period, leaving the
stable period. At higher pixel frequencies, the total cycle time is
shorter, and the stable pixel time becomes shorter as well.
Figure 5. Typical Clamp Configuration
47nF
47nF
47nF
1nF
R
B
G
SOGIN
AIN
AIN
AIN
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Any jitter in the clock reduces the precision with which the
sampling time can be determined and must also be subtracted
from the stable pixel time.
Considerable care has been taken in the design of the
AD9882A’s clock generation circuit to minimize jitter. As
indicated in Figure 7, the clock jitter of the AD9882A is less
than 6% of the total pixel time in all operating modes, making
negligible the reduction in the valid sampling time due to jitter.
The PLL characteristics are determined by the loop filter design,
the PLL charge pump current, and the VCO range setting. The
loop filter design is illustrated in Figure 8. Recommended
settings of VCO range and charge pump current for VESA
standard display modes are listed in Table 10.
10
8
6
4
2
0
25.1 31.5
PIXEL CLOCK
Figure 7. Pixel Clock Jitter vs. Frequency
36.0 40.0 50.0
0.0082µF
Figure 6. Pixel Sampling Times
Figure 8. PLL Loop Filter Detail
PIXEL CLOCK FREQUENCY (MHz)
C
P
INVALID SAMPLE TIMES
FILT
56.2 65.0 75.0
R
2.74kΩ
C
0.082µF
Z
Z
78.7 85.5 94.5 108.0 135.0
PV
D
AD9882A