AD9882AKSTZ-100 Analog Devices Inc, AD9882AKSTZ-100 Datasheet - Page 28

• Manufacturer Part Number: AD9882AKSTZ-100
• Description: IC INTERFACE/DVI 100MHZ 100LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9882AKSTZ-100

• Applications: Video
• Interface: Analog, DVI
• Voltage - Supply: 3.15 V ~ 3.45 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Supply Voltage Range: 3.15V To 3.45V, 2.2V To 3.45V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Msl: MSL 3 - 168 Hours
• Update Rate: 140MSPS
• Bandwidth: 300MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9882A
0x0F 1
This bit is used under two conditions. It is used to select the
active interface when the override bit is set (Register 0x0F,
Bit 2). Alternatively, it is used to determine the active interface
when not overriding but both interfaces are detected.
Table 16. Active Interface Select Settings
AIS
0
1
The default for this register is 0.
0x10 7
This register is used to override the internal circuitry that
determines the polarity of the Hsync signal going into the PLL.
Table 17. Hsync Input Polarity Override Settings
Override Bit
0
1
The default for Hsync polarity override is 0. (Polarity
determined by chip.)
0x10 6
A bit that must be set to indicate the polarity of the Hsync
signal that is applied to the PLL Hsync input.
Table 18. Hsync Input Polarity Settings
HSPOL
0
1
Active low means the leading edge of the Hsync pulse is
negative-going. All PLL timing is based on the leading edge
of Hsync, which is the falling edge. The rising edge is used to
time the internal clamping.
Active high means the leading edge of the Hsync pulse is
positive-going. This means that PLL timing is based on the
leading edge of Hsync, which is now the rising edge.
The device operates if this bit is set incorrectly, but the
internally generated clamp position, as established by clamp
placement (Register 0x05), is not placed as expected, which
might generate clamping errors.
The power-up default value for HSPOL is 1.
AIS Active Interface Select
Hsync Input Polarity Override
HSPOL Hsync Input Polarity
Result
Analog interface
Digital interface
Function
Active low
Active high
Result
Hsync polarity determined by chip.
Hsync polarity determined by Register 0x10,
Bit 6.
Rev. 0 | Page 28 of 40
0x10 5
This bit determines the polarity of the Hsync output and the
SOG output. Table 19 shows the effect of this option. Sync
indicates the logic state of the sync pulse.
Table 19. Hsync Output Polarity Settings
Setting
0
1
The default setting for this register is 0.
0x10 4
This bit is used to override the automatic Hsync selection. To
override, set this bit to Logic 1. When overriding, the active
Hsync is set via Bit 3 in this register.
Table 20. Active Hsync Override Settings
Override
0
1
The default for this register is 0.
0x10 3
This bit is used under two conditions. It is used to select the
active Hsync when the override bit is set (Bit 4). Alternatively, it
is used to determine the active Hsync when not overriding, but
both Hsyncs are detected.
Table 21. Active Hsync Select Settings
Select
0
1
The default for this register is 0.
0x10 2
This bit determines the polarity of the Vsync output. Table 22
shows the effect of this option. SYNC indicates the logic state of
the sync pulse.
Table 22. Vsync Output Polarity Settings
Setting
1
0
The default setting for this register is 0.
0x10 1
This bit is used to override the automatic Vsync selection. To
override, set this bit to Logic 1. When overriding, the active
interface is set via Bit 0 in this register.
Hsync Output Polarity
Active Hsync Override
Active Hsync Select
Vsync Output Polarity
Active Vsync Override
Result
Autodetermines the active Hsync.
Override; Bit 3 determines the active Hsync.
Result
Hsync input
Sync-on-green input
SYNC
Not inverted
Inverted
SYNC
Logic 1 (positive polarity)
Logic 0 (negative polarity)