M95M02-DRMN6TP STMicroelectronics, M95M02-DRMN6TP Datasheet - Page 10

• Manufacturer Part Number: M95M02-DRMN6TP
• Description: IC EEPROM SPI BUS 2MB 8SOIC
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of M95M02-DRMN6TP

• Mfg Application Notes: Make the Most of Serial EEPROMs AppNote
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2M (256K x 8)
• Speed: 5MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11405-2

Connecting to the SPI bus
3
Figure 3.
10/40
SPI Interface with
(CPOL, CPHA) =
CS3
(0, 0) or (1, 1)
SPI Bus Master
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Bus master and memory devices on the SPI bus
1. The Write Protect (W) and Hold (HOLD) signals should be driven high or low as appropriate.
Figure 3
Only one device is selected at a time, so only one device drives the Serial Data Output (Q)
line at a time, the other devices are high impedance.
A pull-up resistor connected on each S input (represented in
device is not selected if the bus master leaves the S line in the high impedance state.
In applications where the bus master might enter a state where the whole input/output SPI
bus is high-impedance at a given time (for example, if the bus master is reset during the
transmission of an instruction), the clock line (C) must be connected to an external pull-
down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high). This ensures that S and C do not become high at the same
time, and so, that the t
CS2 CS1
shows an example of three memory devices connected to an MCU, on an SPI bus.
SDO
SDI
SCK
R
R
SHCH
C Q D
S
SPI Memory
Device
requirement is met.
W
Doc ID 18203 Rev 4
V
CC
HOLD
V
R
SS
C Q D
S
SPI Memory
Device
W
V
HOLD
CC
V
R
SS
Figure
C Q D
S
3) ensures that each
SPI Memory
Device
W
V
CC
HOLD
AI12836b
M95M02-DR
V
SS
V
V
CC
SS