M95M02-DRMN6TP STMicroelectronics, M95M02-DRMN6TP Datasheet - Page 14

• Manufacturer Part Number: M95M02-DRMN6TP
• Description: IC EEPROM SPI BUS 2MB 8SOIC
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of M95M02-DRMN6TP

• Mfg Application Notes: Make the Most of Serial EEPROMs AppNote
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2M (256K x 8)
• Speed: 5MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11405-2

Operating features
4.4
4.5
14/40
Status Register
Figure 6
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See
detailed description of the Status Register bits
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
●
●
●
●
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
●
●
Table 2.
Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be
configured as read-only.
The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status
Register to be protected.
The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
shows the position of the Status Register in the control logic of the device. The
BP1
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write (WRITE) instruction completion
0
0
1
1
Status Register bits
Write-protected block size
Doc ID 18203 Rev 4
BP0
0
1
0
1
Section 6.3: Read Status Register (RDSR)
Protected block
Whole memory
Upper quarter
Upper half
none
3 0000h - 3 FFFFh
2 0000h - 3 FFFFh
0 0000h - 3 FFFFh
Array addresses
protected
none
M95M02-DR
for a