M95M02-DRMN6TP STMicroelectronics, M95M02-DRMN6TP Datasheet - Page 24

• Manufacturer Part Number: M95M02-DRMN6TP
• Description: IC EEPROM SPI BUS 2MB 8SOIC
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of M95M02-DRMN6TP

• Mfg Application Notes: Make the Most of Serial EEPROMs AppNote
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2M (256K x 8)
• Speed: 5MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11405-2

Instructions
6.7
Note:
24/40
Write to Memory Array (WRITE)
As shown in
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. In the case of
latched in, indicating that the instruction is being used to write a single byte. The self-timed
Write cycle starts, and continues for a period t
which the Write in Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven low, as shown in
input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle. The self-
timed Write cycle starts, and continues, for a period t
end of which the Write in Progress (WIP) bit is reset to 0.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size is 256 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
●
●
●
●
The self-timed write cycle, t
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 13. Byte Write (WRITE) sequence
1. As shown in
S
C
D
Q
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
if a Write cycle is already in progress
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Figure
Table
0
1
High Impedance
6, the most significant address bits are Don’t Care.
13, to send this instruction to the device, Chip Select (S) is first driven
Figure
2
Instruction
3
4
13, this occurs after the eighth bit of the data byte has been
W
5
, is internally executed as a sequence of two consecutive
Doc ID 18203 Rev 4
6
7
23
8
14 13
9 10
24-bit address
WC
3
28 29 30 31 32 33 34 35
(as specified in
2
WC
1
(as specified in
0
7
6
Figure
Table
5
Data byte
4
3
12), at the end of
36 37 38
Table
14, the next byte of
2
1
12), at the
M95M02-DR
0
39
AI13879