M95M02-DRMN6TP STMicroelectronics, M95M02-DRMN6TP Datasheet - Page 27

• Manufacturer Part Number: M95M02-DRMN6TP
• Description: IC EEPROM SPI BUS 2MB 8SOIC
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of M95M02-DRMN6TP

• Mfg Application Notes: Make the Most of Serial EEPROMs AppNote
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2M (256K x 8)
• Speed: 5MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11405-2

M95M02-DR
6.9
Figure 16. Read Lock Status sequence
6.10
Read Lock Status
The Read Lock Status instruction (see
locked (or not) in read-only mode. The Read Lock Status sequence is defined with the Chip
Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted
in on Serial Data input (D). Address bit A10 must be 1, all other address bits are Don't Care.
The Lock bit is the LSB (least significant bit) of the byte read on Serial Data output (Q). It is
at ‘1’ when the lock is active and at ‘0’ when the lock is not active. If Chip Select (S)
continues to be driven low, the same data byte is shifted out. The read cycle is terminated by
driving Chip Select (S) high.
Lock ID
The Lock ID instruction permanently locks the Identification Page in read-only mode. Before
this instruction can be accepted, a Write Enable (WREN) instruction must have been
executed. The Lock ID instruction (see
sending the instruction code, the address and a data byte on Serial Data input (D), and
driving Chip Select (S) high. In the address sent, A10 must be equal to 1, all other address
bits are Don't Care. The data byte sent must be equal to the binary value xxxx xx1x, where x
= Don't Care.
Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Lock ID instruction is not executed.
Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write
cycle whose duration is t
W
(specified in
Doc ID 18203 Rev 4
Table
Table
Table
3) is used to check if the Identification Page is
3) is issued by driving Chip Select (S) low,
12).
Instructions
27/40