M95M02-DRMN6TP STMicroelectronics, M95M02-DRMN6TP Datasheet - Page 26

• Manufacturer Part Number: M95M02-DRMN6TP
• Description: IC EEPROM SPI BUS 2MB 8SOIC
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of M95M02-DRMN6TP

• Mfg Application Notes: Make the Most of Serial EEPROMs AppNote
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2M (256K x 8)
• Speed: 5MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11405-2

Instructions
6.8
26/40
Write Identification Page
The Identification Page (256 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. Writing this page is achieved with the Write
Identification Page instruction (see
bits of the instruction byte, address byte, and at least one data byte are then shifted in on
Serial Data input (D). Address bit A10 must be 0, address bits [A23:A11] and [A9:A8] are
Don't Care, the [A7:A0] address bits define the byte address inside the identification page.
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed write cycle triggered by the rising edge of Chip Select (S) continues for
a period t
reset to 0.
In the case of
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S) continues to be driven low, as shown in
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal write cycle. Each time
a new data byte is shifted in, the least significant bits of the internal address counter are
incremented.
The instruction is not accepted, and is not executed, under the following conditions:
●
●
●
●
●
Figure 15. Write Identification Page sequence
if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a
Write Enable instruction)
if Status register bits (BP1, BP0) = (1, 1)
if a write cycle is already in progress
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that was latched in)
if the Identification page is locked by the Lock Status bit
W
(as specified in
Figure
15, Chip Select (S) is driven high after the eighth bit of the data byte
Table
Doc ID 18203 Rev 4
12), at the end of which the Write in Progress (WIP) bit is
Table
3), the Chip Select signal (S) is first driven low. The
Figure
15, the next byte
M95M02-DR