M95M02-DRMN6TP STMicroelectronics, M95M02-DRMN6TP Datasheet - Page 12

• Manufacturer Part Number: M95M02-DRMN6TP
• Description: IC EEPROM SPI BUS 2MB 8SOIC
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of M95M02-DRMN6TP

• Mfg Application Notes: Make the Most of Serial EEPROMs AppNote
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2M (256K x 8)
• Speed: 5MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11405-2

Operating features
4
4.1
4.1.1
4.1.2
4.1.3
12/40
Operating features
Supply voltage (V
Operating supply voltage V
Prior to selecting the memory and issuing instructions to it, a valid and stable V
within the specified [V
must remain stable and valid until the end of the transmission of the instruction and, for a
Write instruction, until the completion of the internal write cycle (t
stable DC supply voltage, it is recommended to decouple the V
capacitor (usually of the order of 10 nF to 100 nF) close to the V
Device reset
In order to prevent inadvertent write operations during power-up, a power on reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until V
reaches the internal reset threshold voltage (this threshold is lower than the minimum V
operating voltage defined in
When V
●
●
●
When V
Power mode. The device must not be accessed until V
voltage within the specified [V
Power-up conditions
When the power supply is turned on, V
time, the Chip Select (S) line is not allowed to float but should follow the V
therefore recommended to connect the S line to V
Figure
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge-
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The V
defined in
in Standby Power mode
deselected (note that, to be executed, an instruction must be preceded by a falling
edge on Chip Select (S))
Status Register value:
–
–
–
CC
3).
CC
CC
voltage has to rise continuously from 0 V up to the minimum V
the Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits)
Table 8
passes over the POR threshold, the device is reset and in the following state:
passes over the POR threshold, the device is reset and enters the Standby
and the rise time must not vary faster than 1 V/µs.
CC
(min), V
CC
Table
CC
)
Doc ID 18203 Rev 4
CC
(min), V
8.
(max)] range must be applied (see
CC
CC
CC
rises continuously from V
(max)] range defined in
CC
via a suitable pull-up resistor (see
CC
reaches a valid and stable V
CC
CC
W
line with a suitable
). In order to secure a
/V
Table
SS
SS
Table
to V
CC
package pins.
8.
CC
operating voltage
CC
8.). This voltage
voltage, it is
. During this
M95M02-DR
CC
voltage
CC
CC
CC