LFE3-95EA-8FN672I Lattice, LFE3-95EA-8FN672I Datasheet - Page 107

• Manufacturer Part Number: LFE3-95EA-8FN672I
• Description: IC FPGA 92KLUTS 380I/O 672-BGA
• Manufacturer: Lattice

Specifications of LFE3-95EA-8FN672I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeECP3 sysCONFIG Port Timing Specifications (Continued)
Figure 3-20. sysCONFIG Parallel Port Read Cycle
t
Master and Slave SPI (Continued)
t
t
t
t
1. Re-toggling the PROGRAMN pin is not permitted until the INITN pin is high. Avoid consecutive toggling of the PROGRAMN.
Master Clock Frequency
Duty Cycle
Parameter
CHHH
CHHL
HHCH
HLQZ
HHQX
Parameter
HOLDN Low Hold Time (Relative to CCLK)
HOLDN High Hold Time (Relative to CCLK)
HOLDN High Setup Time (Relative to CCLK)
HOLDN to Output High-Z
HOLDN to Output Low-Z
WRITEN
CCLK
CS1N
BUSY
D[0:7]
*n = last byte of read cycle.
CSN
Selected value - 15%
Over Recommended Operating Conditions
Min.
40
t
t
SUCS
SUWD
Description
Byte 0
t
BSCL
3-54
Byte 1
t
CORD
Selected value + 15%
Max.
t
60
DCB
DC and Switching Characteristics
t
Byte 2
BSCYC
t
BSCH
LatticeECP3 Family Data Sheet
Byte n*
t
t
HCS
HWD
Min.
—
—
5
5
5
Units
MHz
%
Max.
—
—
—
9
9
Units
ns
ns
ns
ns
ns