LFE3-95EA-8FN672I Lattice, LFE3-95EA-8FN672I Datasheet - Page 43

• Manufacturer Part Number: LFE3-95EA-8FN672I
• Description: IC FPGA 92KLUTS 380I/O 672-BGA
• Manufacturer: Lattice

Specifications of LFE3-95EA-8FN672I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Architecture
Lattice Semiconductor
LatticeECP3 Family Data Sheet
To accomplish write leveling in DDR3, each DQS group has a slightly different delay that is set by DYN DELAY[7:0]
in the DQS Write Control logic block. The DYN DELAY can set 128 possible delay step settings. In addition, the
most significant bit will invert the clock for a 180-degree shift of the incoming clock.
LatticeECP3 input and output registers can also support DDR gearing that is used to receive and transmit the high
speed DDR data from and to the DDR3 Memory.
LatticeECP3 supports the 1.5V SSTL I/O standard required for the DDR3 memory interface. For more information,
refer to the sysIO section of this data sheet.
Please see TN1180,
LatticeECP3 High-Speed I/O Interface
for more information on DDR Memory interface imple-
mentation in LatticeECP3.
sysI/O Buffer
Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysI/O buffers allow users to implement the wide variety
of standards that are found in today’s systems including LVDS, BLVDS, HSTL, SSTL Class I & II, LVCMOS, LVTTL,
LVPECL, PCI.
sysI/O Buffer Banks
LatticeECP3 devices have six sysI/O buffer banks: six banks for user I/Os arranged two per side. The banks on the
bottom side are wraparounds of the banks on the lower right and left sides. The seventh sysI/O buffer bank (Config-
uration Bank) is located adjacent to Bank 2 and has dedicated/shared I/Os for configuration. When a shared pin is
not used for configuration it is available as a user I/O. Each bank is capable of supporting multiple I/O standards.
Each sysI/O bank has its own I/O supply voltage (V
). In addition, each bank, except the Configuration Bank,
CCIO
has voltage references, V
and V
, which allow it to be completely independent from the others. Figure 2-38
REF1
REF2
shows the seven banks and their associated supplies.
In LatticeECP3 devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are pow-
ered using V
. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs inde-
CCIO
pendent of V
.
CCIO
Each bank can support up to two separate V
voltages, V
and V
, that set the threshold for the refer-
REF
REF1
REF2
enced input buffers. Some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin.
Each I/O is individually configurable based on the bank’s supply and reference voltages.
2-40