LFE3-95EA-8FN672I Lattice, LFE3-95EA-8FN672I Datasheet - Page 3

• Manufacturer Part Number: LFE3-95EA-8FN672I
• Description: IC FPGA 92KLUTS 380I/O 672-BGA
• Manufacturer: Lattice

Specifications of LFE3-95EA-8FN672I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Introduction
Lattice Semiconductor
LatticeECP3 Family Data Sheet
Introduction
The LatticeECP3™ (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high perfor-
mance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous
interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture
and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications.
The LatticeECP3 device family expands look-up-table (LUT) capacity to 149K logic elements and supports up to
586 user I/Os. The LatticeECP3 device family also offers up to 320 18x18 multipliers and a wide range of parallel
I/O standards.
The LatticeECP3 FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP3 devices
utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distrib-
uted and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source
synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and
dual-boot capabilities.
The pre-engineered source synchronous logic implemented in the LatticeECP3 device family supports a broad
range of interface standards, including DDR3, XGMII and 7:1 LVDS.
The LatticeECP3 device family also features high speed SERDES with dedicated PCS functions. High jitter toler-
ance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular
data protocols including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit Pre-empha-
sis and Receive Equalization settings make the SERDES suitable for transmission and reception over various
forms of media.
The LatticeECP3 devices also provide flexible, reliable and secure configuration options, such as dual-boot capa-
bility, bit-stream encryption, and TransFR field upgrade features.
®
The Lattice Diamond™ and ispLEVER
design software allows large complex designs to be efficiently imple-
mented using the LatticeECP3 FPGA family. Synthesis library support for LatticeECP3 is available for popular logic
synthesis tools. Diamond and ispLEVER tools use the synthesis tool output along with the constraints from its floor
planning tools to place and route the design in the LatticeECP3 device. The tools extract the timing from the routing
and back-annotate it into the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) modules for the LatticeECP3 family. By using these
configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their
design, increasing their productivity.
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