LFE3-95EA-8FN672I Lattice, LFE3-95EA-8FN672I Datasheet - Page 45

• Manufacturer Part Number: LFE3-95EA-8FN672I
• Description: IC FPGA 92KLUTS 380I/O 672-BGA
• Manufacturer: Lattice

Specifications of LFE3-95EA-8FN672I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
2. Left and Right (Banks 2, 3, 6 and 7) sysI/O Buffer Pairs (50% Differential and 100% Single-Ended Out-
3. Configuration Bank sysI/O Buffer Pairs (Single-Ended Outputs, Only on Shared Pins When Not Used by
Programmable PCI clamps are only available on top banks (PCI clamps are used primarily on inputs and bidirec-
tional pads to reduce ringing on the receiving end) can also be used on inputs.
Typical sysI/O I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when V
levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to
ensure that all other V
all the I/O banks that are critical to the application. For more information about controlling the output logic state with
valid input logic levels during power-up in LatticeECP3 devices, see the list of technical documentation at the end
of this data sheet.
The V
fers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended
that the I/O buffers be powered-up prior to the FPGA core fabric. V
together with the V
Supported sysI/O Standards
The LatticeECP3 sysI/O buffer supports both single-ended and differential standards. Single-ended standards can
be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2V,
1.5V, 1.8V, 2.5V and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individual configuration
options for drive strength, slew rates, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and
open drain. Other single-ended standards supported include SSTL and HSTL. Differential standards supported
include LVDS, BLVDS, LVPECL, MLVDS, RSDS, Mini-LVDS, PPLVDS (point-to-point LVDS), TRLVDS (Transition
Reduced LVDS), differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/O standards (together
with their supply and reference voltages) supported by LatticeECP3 devices. For further information on utilizing the
sysI/O buffer to support a variety of standards please see TN1177,

puts)
The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. One of the
referenced input buffers can also be configured as a differential input. In these banks the two pads in the pair
are described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,
and the comp (complementary) pad is associated with the negative side of the differential I/O. 
In addition, programmable on-chip input termination (parallel or differential, static or dynamic) is supported on
these sides, which is required for DDR3 interface. However, there is no support for hot-socketing for the I/O
pins located on the left and right side of the device as the clamp is always enabled on these pins.

LVDS, RSDS, PPLVDS and Mini-LVDS differential output drivers are available on 50% of the buffer pairs on the
left and right banks.
Configuration)
The sysI/O buffers in the Configuration Bank consist of ratioed single-ended output drivers and single-ended
input buffers. This bank does not support PCI clamp like the other banks on the top, left, and right sides. 

The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
CC
and V
CCAUX
CC
CCIO
supply the power to the FPGA core fabric, whereas the V
and V
banks are active with valid input logic levels to properly control the output logic states of
CCAUX
supplies.
2-42
CC
, V
LatticeECP3 sysIO Usage
CCIO
CCIO8
supplies should be powered-up before or
LatticeECP3 Family Data Sheet
and V
CCIO
CCAUX
supplies power to the I/O buf-
have reached satisfactory
Guide.
Architecture