LFE3-95EA-8FN672I Lattice, LFE3-95EA-8FN672I Datasheet - Page 72

LFE3-95EA-8FN672I

Manufacturer Part Number

LFE3-95EA-8FN672I

Description

IC FPGA 92KLUTS 380I/O 672-BGA

Manufacturer

Lattice

Datasheet

1.LFE3-150EA-7FN672C.pdf (136 pages)

Specifications of LFE3-95EA-8FN672I

Lead Free Status / Rohs Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

LFE3-95EA-8FN672I

Manufacturer:

Lattice Semiconductor Corporation

Quantity:

10 000

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Lattice Semiconductor

LatticeECP3 External Switching Characteristics (Continued)

Generic DDRX1 Inputs with Clock and Data (>10 Bits Wide) Aligned at Pin (GDDRX1_RX.SCLK.Aligned) Using DLL -

CLKIN Pin for Clock Input

Data Left, Right and Top Sides and Clock Left and Right Sides

Generic DDRX1 Inputs with Clock and Data (<10 Bits Wide) Centered at Pin (GDDRX1_RX.DQS.Centered) Using DQS

Pin for Clock Input

Generic DDRX1 Inputs with Clock and Data (<10bits wide) Aligned at Pin (GDDRX1_RX.DQS.Aligned) Using DQS Pin

for Clock Input

Data and Clock Left and Right Sides

Generic DDRX2 Inputs with Clock and Data (>10 Bits Wide) Centered at Pin (GDDRX2_RX.ECLK.Centered) Using

PCLK Pin for Clock Input

Left and Right Sides

Generic DDRX2 Inputs with Clock and Data (>10 Bits Wide) Aligned at Pin (GDDRX2_RX.ECLK.Aligned)

Left and Right Side Using DLLCLKIN Pin for Clock Input

MAX_GDDR

DVACLKGDDR

DVECLKGDDR

MAX_GDDR

SUGDDR

HOGDDR

MAX_GDDR

DVACLKGDDR

DVECLKGDDR

MAX_GDDR

SUGDDR

HOGDDR

MAX_GDDR

SUGDDR

HOGDDR

MAX_GDDR

SUGDDR

HOGDDR

MAX_GDDR

SUGDDR

HOGDDR

MAX_GDDR

DVACLKGDDR

DVECLKGDDR

MAX_GDDR

DVACLKGDDR

DVECLKGDDR

MAX_GDDR

DVACLKGDDR

DVECLKGDDR

Parameter

DDRX1 Clock Frequency

Data Setup Before CLK

Data Hold After CLK

DDRX1 Clock Frequency

Data Setup After CLK

Data Hold After CLK

DDRX1 Clock Frequency

Data Setup Before CLK

Data Hold After CLK

DDRX1 Clock Frequency

Data Setup Before CLK

Data Hold After CLK

DDRX2 Clock Frequency

Data Setup Before CLK

Data Hold After CLK

DDRX2 Clock Frequency

Data Setup Before CLK

Data Hold After CLK

DDRX2 Clock Frequency

Data Setup Before CLK

Data Hold After CLK

DDRX2 Clock Frequency

Data Setup Before CLK

Data Hold After CLK

DDRX2 Clock Frequency

Data Setup Before CLK

Data Hold After CLK

DDRX2 Clock Frequency

Data Setup Before CLK

Data Hold After CLK

Over Recommended Commercial Operating Conditions

Description

All ECP3EA Devices

All ECP3EA Devices 0.775

All ECP3EA Devices

All ECP3EA Devices 535

All ECP3EA Devices

All ECP3EA Devices 0.775

All ECP3EA Devices

ECP3-150EA

ECP3-70EA/95EA

ECP3-35EA

ECP3-17EA

ECP3-150EA

ECP3-70EA/95EA

ECP3-35EA

3-19

Device

DC and Switching Characteristics

0.775

0.790

Min. Max. Min. Max. Min. Max.

321

335

—

LatticeECP3 Family Data Sheet

-8

0.225

0.210

250

405

460

—

0.775

0.790

535

403

425

—

-7

0.225

0.210

1, 2

250

325

385

—

0.775

0.790

535

471

535

—

-6

0.225

0.210

250

280

250

345

311

—

Units

MHz

LFE3-95EA-8FN672I Lattice, LFE3-95EA-8FN672I Datasheet - Page 72

LFE3-95EA-8FN672I

Specifications of LFE3-95EA-8FN672I

Available stocks

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