LFE3-95EA-8FN672I Lattice, LFE3-95EA-8FN672I Datasheet - Page 71

• Manufacturer Part Number: LFE3-95EA-8FN672I
• Description: IC FPGA 92KLUTS 380I/O 672-BGA
• Manufacturer: Lattice

Specifications of LFE3-95EA-8FN672I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeECP3 External Switching Characteristics (Continued)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Generic DDR
Generic DDRX1 Inputs with Clock and Data (>10 Bits Wide) Centered at Pin (GDDRX1_RX.SCLK.Centered) Using
PCLK Pin for Clock Input
t
t
f
Generic DDRX1 Inputs with Clock and Data (>10 Bits Wide) Aligned at Pin (GDDRX1_RX.SCLK.PLL.Aligned) Using
PLLCLKIN Pin for Clock Input
Data Left, Right, and Top Sides and Clock Left and Right Sides
t
t
HPLL
SU_DELPLL
H_DELPLL
COPLL
SUPLL
HPLL
SU_DELPLL
H_DELPLL
COPLL
SUPLL
HPLL
SU_DELPLL
H_DELPLL
COPLL
SUPLL
HPLL
SU_DELPLL
H_DELPLL
SUGDDR
HOGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
Parameter
12
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Clock to Data Hold - PIO Input
Register with Input Data Delay
Data Setup Before CLK
Data Hold After CLK
DDRX1 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
Over Recommended Commercial Operating Conditions
Description
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
All ECP3EA Devices 480
All ECP3EA Devices 480
All ECP3EA Devices
All ECP3EA Devices
All ECP3EA Devices 0.775
3-18
Device
DC and Switching Characteristics
Min. Max. Min. Max. Min. Max.
0.8
1.6
0.7
0.7
1.6
0.0
0.6
0.3
1.6
0.0
0.6
0.3
1.6
0.0
—
—
—
—
—
—
LatticeECP3 Family Data Sheet
-8
0.225
250
0.0
2.4
2.3
2.1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.775
480
480
0.9
1.8
0.8
0.7
1.8
0.0
0.7
0.3
1.7
0.0
0.7
0.3
1.7
0.0
—
—
—
—
—
—
-7
0.225
1, 2
250
0.0
2.6
2.5
2.3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.775
480
480
1.0
2.0
0.9
0.8
2.0
0.0
0.8
0.4
1.8
0.0
0.8
0.4
1.8
0.0
—
—
—
—
—
—
-6
0.225
250
0.0
2.9
2.7
2.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
UI
UI