LFE3-95EA-8FN672I Lattice, LFE3-95EA-8FN672I Datasheet - Page 52

• Manufacturer Part Number: LFE3-95EA-8FN672I
• Description: IC FPGA 92KLUTS 380I/O 672-BGA
• Manufacturer: Lattice

Specifications of LFE3-95EA-8FN672I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Soft Error Detect (SED) Support
LatticeECP3 devices have dedicated logic to perform Cycle Redundancy Code (CRC) checks. During configura-
tion, the configuration data bitstream can be checked with the CRC logic block. In addition, the LatticeECP3 device
can also be programmed to utilize a Soft Error Detect (SED) mode that checks for soft errors in configuration
SRAM. The SED operation can be run in the background during user mode. If a soft error occurs, during user
mode (normal operation) the device can be programmed to generate an error signal.
For further information on SED support, please see TN1184,
Guide.
External Resistor
LatticeECP3 devices require a single external, 10K ohm ±1% value between the XRES pin and ground. Device
configuration will not be completed if this resistor is missing. There is no boundary scan register on the external
resistor pad.
On-Chip Oscillator
Every LatticeECP3 device has an internal CMOS oscillator which is used to derive a Master Clock (MCCLK) for
configuration. The oscillator and the MCCLK run continuously and are available to user logic after configuration is
completed. The software default value of the MCCLK is nominally 2.5MHz. Table 2-16 lists all the available MCCLK
frequencies. When a different Master Clock is selected during the design process, the following sequence takes
place:
1. Device powers up with a nominal Master Clock frequency of 3.1MHz.
2. During configuration, users select a different master clock frequency.
3. The Master Clock frequency changes to the selected frequency once the clock configuration bits are received.
4. If the user does not select a master clock frequency, then the configuration bitstream defaults to the MCCLK
This internal CMOS oscillator is available to the user by routing it as an input clock to the clock tree. For further
information on the use of this oscillator for configuration or user mode, please see TN1169,
FIG Usage
Table 2-16. Selectable Master Clock (MCCLK) Frequencies During Configuration (Nominal)
system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded
remotely and stored in a separate location in the configuration storage device. Any time after the update the
LatticeECP3 can be re-booted from this new configuration file. If there is a problem, such as corrupt data dur-
ing download or incorrect version number with this new boot image, the LatticeECP3 device can revert back to
the original backup golden configuration and try again. This all can be done without power cycling the system.
For more information, please see TN1169,
frequency of 2.5MHz.
Guide.
1. Software default MCCLK frequency. Hardware default is 3.1MHz.
2. Maximum MCCLK with encryption enabled.
3. Maximum MCCLK without encryption.
MCCLK (MHz)
2.5
4.3
5.4
6.9
8.1
9.2
1
LatticeECP3 sysCONFIG Usage
2-49
MCCLK (MHz)
LatticeECP3 Soft Error Detection (SED) Usage
15
33
10
13
20
26
2
3
LatticeECP3 Family Data Sheet
Guide.
LatticeECP3 sysCON-
Architecture