LFE3-95EA-8FN672I Lattice, LFE3-95EA-8FN672I Datasheet - Page 135

• Manufacturer Part Number: LFE3-95EA-8FN672I
• Description: IC FPGA 92KLUTS 380I/O 672-BGA
• Manufacturer: Lattice

Specifications of LFE3-95EA-8FN672I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
December 2010
April 2011
(cont.)
Date
Version
01.7EA
01.8EA
(cont.)
Pinout Information
DC and Switching
Characteristics
Architecture
Architecture
Introduction
Section
Corrected number of user I/Os
Corrected the package type in Table 2-14 Available SERDES Quad per
LatticeECP3 Devices.
Updated description of General Purpose PLL
Added additional information in the Flexible Quad SERDES Architecture
section.
Added footnotes and corrected the information in Table 2-16 Selectable
master Clock (MCCLK) Frequencies During Configuration (Nominal).
Updated Figure 2-16, Per Region Secondary Clock Selection.
Updated description for On-Chip Programmable Termination.
Added information about number of rows of DSP slices.
Updated footnote 2 for Table 2-12, On-Chip Termination Options for
Input Modes.
Updated information for sysIO buffer pairs.
Corrected minimum number of General Purpose PLLs (was 4, now 2).
Regenerated sysCONFIG Port Timing figure.
Added t
table.
Corrected units, revised and added data, and corrected footnote 1 in
External Switching Characteristics table.
Added Jitter Transfer figures in SERDES External Reference Clock sec-
tion.
Corrected capacitance information in the DC Electrical Characteristics
table.
Corrected data in the Register-to-Register Performance table.
Corrected GDDR Parameter name HOGDDR.
Corrected RSDS25 -7 data in Family Timing Adders table.
Added footnotes 10-12 to DDR data information in the External Switch-
ing Characteristics table.
Corrected titles for Figures 3-7 (DDR/DDR2/DDR3 Parameters) and 
3-8 (Generic DDR/DDRX2 Parameters).
Updated titles for Figures 3-5 (MLVDS25 (Multipoint Low Voltage Differ-
ential Signaling)) and 3-6 (Generic DDRX1/DDRX2 (With Clock and
Data Edges Aligned)).
Updated Supply Current table.
Added GDDR interface information to the External Switching and Char-
acteristics table.
Added footnote to sysIO Recommended Operating Conditions table.
Added footnote to LVDS25 table.
Corrected DDR section footnotes and references.
Corrected Hot Socketing support from “top and bottom banks” to “top
and bottom I/O pins”.
Updated description for VTTx.
Updated Secondary Clock/Control Sources text section.
7-4
W
(clock pulse width) in External Switching Characteristics
Change Summary
LatticeECP3 Family Data Sheet
Revision History