LFE3-95EA-8FN672I Lattice, LFE3-95EA-8FN672I Datasheet - Page 14

• Manufacturer Part Number: LFE3-95EA-8FN672I
• Description: IC FPGA 92KLUTS 380I/O 672-BGA
• Manufacturer: Lattice

Specifications of LFE3-95EA-8FN672I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-8. Clock Divider Connections
Clock Distribution Network
LatticeECP3 devices have eight quadrant-based primary clocks and eight secondary clock/control sources. Two
high performance edge clocks are available on the top, left, and right edges of the device to support high speed
interfaces. These clock sources are selected from external I/Os, the sysCLOCK PLLs, DLLs or routing. These clock
sources are fed throughout the chip via a clock distribution system.
Primary Clock Sources
LatticeECP3 devices derive clocks from six primary source types: PLL outputs, DLL outputs, CLKDIV outputs, ded-
icated clock inputs, routing and SERDES Quads. LatticeECP3 devices have two to ten sysCLOCK PLLs and two
DLLs, located on the left and right sides of the device. There are six dedicated clock inputs: two on the top side, two
on the left side and two on the right side of the device. Figures 2-9, 2-10 and 2-11 show the primary clock sources
for LatticeECP3 devices.
Figure 2-9. Primary Clock Sources for LatticeECP3-17
DLL Input
PLL Input
Clock
Clock
Input
Input
CLKOP (PLL)
CLKOP (DLL)
DLL
PLL
CLK
DIV
Note: Clock inputs can be configured in differential or single-ended mode.
ECLK1
ECLK2
RELEASE
From Routing
Clock Input
to Eight Quadrant Clock Selection
RST
Primary Clock Sources
Clock Input
2-11
SERDES
Quad
From Routing
CLKDIV
LatticeECP3 Family Data Sheet
CLK
DLL
DIV
PLL
÷1
÷2
÷4
÷8
Clock
Input
Clock
Input
DLL Input
PLL Input
Architecture