LFE3-95EA-8FN672I Lattice, LFE3-95EA-8FN672I Datasheet - Page 26

• Manufacturer Part Number: LFE3-95EA-8FN672I
• Description: IC FPGA 92KLUTS 380I/O 672-BGA
• Manufacturer: Lattice

Specifications of LFE3-95EA-8FN672I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-25. Detailed sysDSP Slice Diagram
The LatticeECP2 sysDSP block supports the following basic elements.
Table 2-8 shows the capabilities of each of the LatticeECP3 slices versus the above functions.
Table 2-8. Maximum Number of Elements in a Slice
Some options are available in the four elements. The input register in all the elements can be directly loaded or can
be loaded as a shift register from previous operand registers. By selecting “dynamic operation” the following opera-
tions are possible:
• MULT (Multiply)
• MAC (Multiply, Accumulate)
• MULTADDSUB (Multiply, Addition/Subtraction)
• MULTADDSUBSUM (Multiply, Addition/Subtraction, Summation)
• In the Add/Sub option the Accumulator can be switched between addition and subtraction on every cycle.
• The loading of operands can switch between parallel and serial operations.
DSP Slice
Previous
1. One slice can implement 1/2 9x9 m9x9addsubsum and two m9x9addsubsum with two slices.
MULTADDSUBSUM
Width of Multiply
MULTADDSUB
IR = Input Register
PR = Pipeline Register
OR = Output Register
FR = Flag Register
Note: A_ALU, B_ALU and C_ALU are internal signals generated by combining bits from AA, AB, BA BB and C
inputs. See TN1182, LatticeECP3 sysDSP Usage Guide, for further information.
Rounding
SRIB
SRIA
C_ALU
A_ALU
MULT
MAC
CIN
0
IR
C
IR
AA
MULTA
OR
PR
x9
1
4
1
2
AMUX
A_ALU
1
IR
From FPGA Core
AB
To FPGA Core
0
R = Logic (B, C)
R= A ± B ± C
2-23
OR
PR
IR
OPCODE
FR
0
=
=
x18
1/2
B_ALU
BMUX
2
1
1
IR
ALU
BA
MULTB
LatticeECP3 Family Data Sheet
OR
PR
IR
BB
IR
COUT
SROB
SROA
x36
1/2
—
—
—
DSP Slice
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Architecture