LFE3-95EA-8FN672I Lattice, LFE3-95EA-8FN672I Datasheet - Page 50

• Manufacturer Part Number: LFE3-95EA-8FN672I
• Description: IC FPGA 92KLUTS 380I/O 672-BGA
• Manufacturer: Lattice

Specifications of LFE3-95EA-8FN672I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
The Diamond and ispLEVER design tools support all modes of the PCS. Most modes are dedicated to applications
associated with a specific industry standard data protocol. Other more general purpose modes allow users to
define their own operation. With these tools, the user can define the mode for each quad in a design.
Popular standards such as 10Gb Ethernet, x4 PCI Express and 4x Serial RapidIO can be implemented using IP
(available through Lattice), a single quad (Four SERDES channels and PCS) and some additional logic from the
core.
The LatticeECP3 family also supports a wide range of primary and secondary protocols. Within the same quad, the
LatticeECP3 family can support mixed protocols with semi-independent clocking as long as the required clock fre-
quencies are integer x1, x2, or x11 multiples of each other. Table 2-15 lists the allowable combination of primary
and secondary protocol combinations.
Flexible Quad SERDES Architecture
The LatticeECP3 family SERDES architecture is a quad-based architecture. For most SERDES settings and stan-
dards, the whole quad (consisting of four SERDES) is treated as a unit. This helps in silicon area savings, better
utilization and overall lower cost.
However, for some specific standards, the LatticeECP3 quad architecture provides flexibility; more than one stan-
dard can be supported within the same quad.
Table 2-15 shows the standards can be mixed and matched within the same quad. In general, the SERDES stan-
dards whose nominal data rates are either the same or a defined subset of each other, can be supported within the
same quad. In Table 2-15, the Primary Protocol column refers to the standard that determines the reference clock
and PLL settings. The Secondary Protocol column shows the other standard that can be supported within the
same quad.
Furthermore, Table 2-15 also implies that more than two standards in the same quad can be supported, as long as
they conform to the data rate and reference clock requirements. For example, a quad may contain PCI Express 1.1,
SGMII, Serial RapidIO Type I and Serial RapidIO Type II, all in the same quad.
Table 2-15. LatticeECP3 Primary and Secondary Protocol Support
There are some restrictions to be aware of when using spread spectrum. When a quad shares a PCI Express x1
channel with a non-PCI Express channel, ensure that the reference clock for the quad is compatible with all proto-
cols within the quad. For example, a PCI Express spread spectrum reference clock is not compatible with most
Gigabit Ethernet applications because of tight CTC ppm requirements.
While the LatticeECP3 architecture will allow the mixing of a PCI Express channel and a Gigabit Ethernet, Serial
RapidIO or SGMII channel within the same quad, using a PCI Express spread spectrum clocking as the transmit
PCI Express 1.1
PCI Express 1.1
PCI Express 1.1
PCI Express 1.1
Serial RapidIO Type I
Serial RapidIO Type I
Serial RapidIO Type II
Serial RapidIO Type II
Serial RapidIO Type II
CPRI-3
3G-SDI
Primary Protocol
2-47
SGMII
Gigabit Ethernet
Serial RapidIO Type I
Serial RapidIO Type II
SGMII
Gigabit Ethernet
SGMII
Gigabit Ethernet
Serial RapidIO Type I
CPRI-2 and CPRI-1
HD-SDI and SD-SDI
Secondary Protocol
LatticeECP3 Family Data Sheet
Architecture