LFE3-95EA-8FN672I Lattice, LFE3-95EA-8FN672I Datasheet - Page 23

• Manufacturer Part Number: LFE3-95EA-8FN672I
• Description: IC FPGA 92KLUTS 380I/O 672-BGA
• Manufacturer: Lattice

Specifications of LFE3-95EA-8FN672I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Single, Dual and Pseudo-Dual Port Modes
In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output.
EBR memory supports the following forms of write behavior for single port or dual port operation:
1. Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current
2. Write Through – A copy of the input data appears at the output of the same port during a write cycle. This
3. Read-Before-Write (EA devices only) – When new data is written, the old content of the address appears at
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A
and Port B, respectively. The Global Reset (GSRN) signal can reset both ports. The output data latches and asso-
ciated resets for both ports are as shown in Figure 2-22.
Figure 2-22. Memory Core Reset
For further information on the sysMEM EBR block, please see the list of technical documentation at the end of this
data sheet.
sysDSP™ Slice
The LatticeECP3 family provides an enhanced sysDSP architecture, making it ideally suited for low-cost, high-per-
formance Digital Signal Processing (DSP) applications. Typical functions used in these applications are Finite
Impulse Response (FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convo-
lution encoders and decoders. These complex signal processing functions use similar building blocks such as mul-
tiply-adders and multiply-accumulators.
sysDSP Slice Approach Compared to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with
fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by
higher clock speeds. The LatticeECP3, on the other hand, has many DSP slices that support different data widths.
address) does not appear on the output. This mode is supported for all data widths.
mode is supported for all data widths.
the output. This mode is supported for x9, x18, and x36 data widths.
GSRN
RSTA
RSTB
Programmable Disable
Memory Core
2-20
Output Data
L
L
D
D
Latches
CLR
CLR
SET
SET
Q
Q
LatticeECP3 Family Data Sheet
Port A[17:0]
Port B[17:0]
Architecture