LFE3-95EA-8FN672I Lattice, LFE3-95EA-8FN672I Datasheet - Page 51

• Manufacturer Part Number: LFE3-95EA-8FN672I
• Description: IC FPGA 92KLUTS 380I/O 672-BGA
• Manufacturer: Lattice

Specifications of LFE3-95EA-8FN672I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
reference clock will cause a violation of the Gigabit Ethernet, Serial RapidIO and SGMII transmit jitter specifica-
tions.
For further information on SERDES, please see TN1176,
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeECP3 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test
Access Port (TAP). This allows functional testing of the circuit board on which the device is mounted through a
serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to
be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test
access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage
V
For more information, please see TN1169,
Device Configuration
All LatticeECP3 devices contain two ports that can be used for device configuration. The Test Access Port (TAP),
which supports bit-wide configuration, and the sysCONFIG port, support dual-byte, byte and serial configuration.
The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-
System Configuration specification. The sysCONFIG port includes seven I/Os used as dedicated pins with the
remaining pins used as dual-use pins. See TN1169,
about using the dual-use pins as general purpose I/Os.
There are various ways to configure a LatticeECP3 device:
1. JTAG
2. Standard Serial Peripheral Interface (SPI and SPIm modes) - interface to boot PROM memory
3. System microprocessor to drive a x8 CPU port (PCM mode)
4. System microprocessor to drive a serial slave SPI port (SSPI mode)
5. Generic byte wide flash with a MachXO™ device, providing control and addressing
On power-up, the FPGA SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration
port is selected, it will remain active throughout that configuration cycle. The IEEE 1149.1 port can be activated any
time after power-up by sending the appropriate command through the TAP port.
LatticeECP3 devices also support the Slave SPI Interface. In this mode, the FPGA behaves like a SPI Flash device
(slave mode) with the SPI port of the FPGA to perform read-write operations.
Enhanced Configuration Options
LatticeECP3 devices have enhanced configuration features such as: decryption support, TransFR™ I/O and dual-
boot image support.
1. TransFR (Transparent Field Reconfiguration)
2. Dual-Boot Image Support
CCJ
TransFR I/O (TFR) is a unique Lattice technology that allows users to update their logic in the field without
interrupting system operation using a single ispVM command. TransFR I/O allows I/O states to be frozen dur-
ing device configuration. This allows the device to be field updated with a minimum of system disruption and
downtime. See TN1087,
details.
Dual-boot images are supported for applications requiring reliable remote updates of configuration data for the
and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.
Minimizing System Interruption During Configuration Using TransFR Technology
LatticeECP3 sysCONFIG Usage
LatticeECP3 sysCONFIG Usage Guide
2-48
LatticeECP3 SERDES/PCS Usage
LatticeECP3 Family Data Sheet
Guide.
Guide.
for more information
Architecture
for