LFE3-95EA-8FN672I Lattice, LFE3-95EA-8FN672I Datasheet - Page 76

• Manufacturer Part Number: LFE3-95EA-8FN672I
• Description: IC FPGA 92KLUTS 380I/O 672-BGA
• Manufacturer: Lattice

Specifications of LFE3-95EA-8FN672I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeECP3 External Switching Characteristics (Continued)
t
f
DDR3 Clock Timing
t
t
t
t
1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Diamond or ispLEVER soft-
2. General I/O timing numbers based on LVCMOS 2.5, 12mA, Fast Slew Rate, 0pf load.
3. Generic DDR timing numbers based on LVDS I/O.
4. DDR timing numbers based on SSTL25. DDR2 timing numbers based on SSTL18.
5. DDR3 timing numbers based on SSTL15.
6. Uses LVDS I/O standard.
7. The current version of software does not support per bank skew numbers; this will be supported in a future release.
8. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment.
9. Using settings generated by IPexpress.
10. These numbers are generated using best case PLL located in the center of the device.
11. Uses SSTL25 Class II Differential I/O Standard.
12. All numbers are generated with ispLEVER 8.1 software.
DQVAS
MAX_DDR3
CH
CL
JIT
JIT
Parameter
(avg)
ware.
(per, lck)
(cc, lck)
(avg)
9
9
9
9
Data Valid After DQS
DDR3 clock frequency
Average High Pulse Width
Average Low Pulse Width
Output Clock Period Jitter During
DLL Locking Period
Output Cycle-to-Cycle Period Jitter
During DLL Locking Period
Over Recommended Commercial Operating Conditions
Description
All ECP3 Devices
All ECP3 Devices
All ECP3 Devices
All ECP3 Devices
All ECP3 Devices
All ECP3 Devices
3-23
Device
DC and Switching Characteristics
Min. Max. Min. Max. Min. Max.
0.25
0.47
0.47
300
-90
—
LatticeECP3 Family Data Sheet
-8
0.53
0.53
400
180
90
—
0.25
0.47
0.47
266
-90
—
-7
1, 2
0.53
0.53
180
333
90
—
0.25
0.47
0.47
266
-90
—
-6
0.53
0.53
300
180
90
—
Units
MHz
UI
UI
UI
ps
ps