GE28F320C3BD70

Manufacturer Part NumberGE28F320C3BD70
ManufacturerIntel
GE28F320C3BD70 datasheet
 


Specifications of GE28F320C3BD70

Density32MbAccess Time (max)70ns
Interface TypeParallelBoot TypeBottom
Address Bus21bOperating Supply Voltage (typ)3/3.3V
Operating Temp Range-40C to 85CPackage TypeVFBGA
Sync/asyncAsynchronousOperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size16bNumber Of Words2M
Supply Current18mAMountingSurface Mount
Pin Count48Lead Free Status / Rohs StatusNot Compliant
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Numonyx™ Advanced+ Boot Block Flash
Memory (C3)
28F800C3, 28F160C3, 28F320C3 (x16)
Product Features
Flexible SmartVoltage Technology
— 2.7 V– 3.6 V read/program/erase
— 12 V for fast production programming
1.65 V to 2.5 V or 2.7 V to 3.6 V I/O Option
— Reduces overall system power
High Performance
— 2.7 V– 3.6 V: 70 ns max access time
Optimized Architecture for Code Plus Data
Storage
— Eight 4 Kword blocks, top or bottom
parameter boot
— Up to 127 x 32 Kword blocks
— Fast program suspend capability
— Fast erase suspend capability
Flexible Block Locking
— Lock/unlock any block
— Full protection on power-up
— Write Protect (WP#) pin for hardware block
protection
Low Power Consumption
— 9 mA typical read
— 7 uA typical standby with Automatic Power
Savings feature
Extended Temperature Operation
— -40 °C to +85 °C
128-bit Protection Register
— 64 bit unique device identifier
— 64 bit user programmable OTP cells
Extended Cycling Capability
— Minimum 100,000 block erase cycles
Software
— Supported by Numonyx Advanced Flash
File Managers -- Numonyx™ VFM,
Numonyx™ FDI, etc.
— Code and data storage in the same
memory device
— Robust Power Loss Recovery for Data Loss
Prevention
— Common Flash Interface
Standard Surface Mount Packaging
— 48-Ball μBGA*/VFBGA
— 64-Ball Easy BGA packages
— 48-TSOP package
Intel ETOX* VIII (0.13 μm) Flash Technology
— 8, 16, 32 Mbit
Intel ETOX* VII (0.18 μm) Flash Technology
— 16, 32 Mbit
Intel ETOX* VI (0.25 μm) Flash Technology
— 8, 16 and 32 Mbit
Datasheet
290645-24
March 2008

GE28F320C3BD70 Summary of contents

  • Page 1

    ... Easy BGA packages — 48-TSOP package Intel ETOX* VIII (0.13 μm) Flash Technology — 8, 16, 32 Mbit Intel ETOX* VII (0.18 μm) Flash Technology — 16, 32 Mbit Intel ETOX* VI (0.25 μm) Flash Technology — and 32 Mbit Datasheet 290645-24 March 2008 ...

  • Page 2

    ... Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice. Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “ ...

  • Page 3

    C3 Discrete Contents 1.0 Introduction .............................................................................................................. 7 1.1 Nomenclature ..................................................................................................... 7 1.2 Conventions ....................................................................................................... 8 2.0 Functional Overview .................................................................................................. 9 2.1 Product Overview ................................................................................................ 9 2.2 Block Diagram .................................................................................................. 10 2.3 Memory Map..................................................................................................... 10 3.0 Package Information ............................................................................................... 13 3.1 ...

  • Page 4

    Read Mode........................................................................................................41 10.1.1 Read Array ............................................................................................41 10.1.2 Read Identifier .......................................................................................41 10.1.3 CFI Query ..............................................................................................42 10.1.4 Read Status Register...............................................................................42 10.1.4.1 Clear Status Register .................................................................43 10.2 Program Mode...................................................................................................43 10.2.1 12-Volt Production Programming ..............................................................43 10.2.2 Suspending and Resuming Program ..........................................................44 10.3 Erase ...

  • Page 5

    ... Byte-Wide Protection Register Address change 10/03/98 -003 I CCS Added Command Sequence Error Note (Table 7) Datasheet renamed from 3 Volt Advanced Boot Block, 8-, 16-, 32-Mbit Flash Memory Family. Added t 12/04/98 -004 Programming the Protection Register clarification (Section 3.4.2) 12/31/98 -005 Removed all references to x8 configurations 02/24/99 ...

  • Page 6

    Date of Version Revision 10/01/03 -017 Corrected information in the Device Geometry Details table, address 0x34. 5/20/04 -018 Updated the layout of the datasheet. 9/1/04 -019 Fixed typo for Standby power on cover page. 9/14/04 -020 Added lead-free line items ...

  • Page 7

    ... The Numonyx™ Advanced+ Book Block Flash Memory (C3) device, manufactured on Intel’s latest 0.13 μm and 0.18 μm technologies, represents a feature-rich solution for low-power applications. The C3 device incorporates low-voltage capability (3 V read, program, and erase) with high-speed, low-power operation. Flexible block locking allows any block to be independently locked or unlocked. Add to this the Numonyx™ ...

  • Page 8

    Conventions The terms pin and signal are often used interchangeably to refer to the external signal connections on the package; for chip scale package (CSP) the term ball is used. Group Membership Brackets: Square brackets will be used to ...

  • Page 9

    ... C3 Discrete 2.0 Functional Overview This section provides an overview of the Numonyx™ Advanced+ Boot Block Flash Memory (C3) device features and architecture. 2.1 Product Overview The C3 flash memory device provides high-performance asynchronous reads in package-compatible densities with a 16 bit data bus. Individually-erasable memory blocks are optimally sized for code and data storage. Eight 4 Kword parameter blocks are located in the boot block at either the top or bottom of the device’ ...

  • Page 10

    ... Memory Map The C3 Discrete device is asymmetrically blocked, which enables system code and data integration within a single flash device. The bulk of the array is divided into 32 Kword main blocks that can store code or data, and 4 Kword boot blocks to facilitate storage of boot code or for frequently changing small parameters. See Memory Map” ...

  • Page 11

    C3 Discrete Table 1: Top Boot Memory Map 8-Mbit Size Size Memory (KW Blk (KW Addressin ) ) g (Hex) 7F000 7FFFF 7E000 7EFFF 7D000 7DFFF 7C000 7CFFF ...

  • Page 12

    Table 2: Bottom Boot Memory Map 8-Mbit Size Size Memory (KW Blk (KW Addressin ) ) g (Hex) 78000 7FFFF 70000 77FFF 68000 6FFFF 60000 67FFF ... ... ...

  • Page 13

    C3 Discrete 3.0 Package Information 3.1 μBGA* and VF BGA Package μ Figure 2: BGA* and VF BGA Package Drawing and Dimensions Ball A1 Corner Top View - Bump Side ...

  • Page 14

    TSOP Package Figure 3: TSOP Package Drawing and Dimensions Z Pin 1 Detail B b Notes: 1. One dimple on package denotes Pin two dimples, then the larger dimple denotes Pin 1. 3. Pin 1 will ...

  • Page 15

    C3 Discrete 3.3 Easy BGA Package Figure 4: Easy BGA Package Drawing and Dimension Ball A1 Corner Top View - Ball side down A1 A2 Dimensions Table Package Height ...

  • Page 16

    Ballout and Signal Descriptions The C3 device is available in 48-lead TSOP, 48-ball VF BGA, 48-ball μBGA, and Easy BGA packages. See page 19, respectively. 4.1 48-Lead TSOP Package Figure 5: 48-Lead TSOP Package ...

  • Page 17

    C3 Discrete Figure 6: Mark for Pin-1 Indicator on 48-Lead 8-Mb, 16-Mb and 32-Mb TSOP Current M ark: New M ark: Note: The topside marking on 8 Mb, 16 Mb, and 32 Mb Numonyx™ Advanced and Advanced + Boot Block ...

  • Page 18

    Figure 7: 48-Ball µBGA* and 48-Ball VF BGA Chip Scale Package (Top View, Ball 1,2,3 Down A13 A11 B A14 A10 C A15 A12 D A16 D14 E V D15 CCQ F GND D7 Notes: 1. Shaded connections ...

  • Page 19

    C3 Discrete 4.2 64-Ball Easy BGA Package Figure 8: 64-Ball Easy BGA Package ( RP ...

  • Page 20

    Table 5: Signal Descriptions Symbol Type WRITE ENABLE: Active-low input. WE# controls writes to the device. Address and data are latched on WE# Input the rising edge of the WE# pulse. WRITE PROTECT: Active-low input. When WP logic ...

  • Page 21

    C3 Discrete 5.0 Maximum Ratings and Operating Conditions 5.1 Absolute Maximum Ratings Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These ratings are stress ratings only. Operation beyond the “Operating Conditions” is not recommended, and ...

  • Page 22

    Table 6: Temperature and Voltage Operating Conditions Symbol Parameter V PP2 Cycling Block Erase Cycling Notes and V must share the same supply when they are in the V CC CCQ 2. V Max = 3.3 V for ...

  • Page 23

    C3 Discrete 6.0 Electrical Specifications 6.1 Current Characteristics Table 7: DC Current Characteristics (Sheet Sym Parameter V CCQ Note I Input Load Current 1,2 LI Output Leakage I 1,2 LO Current V Standby Current CC ...

  • Page 24

    Table 7: DC Current Characteristics (Sheet Sym Parameter V CCQ Note I V Program Current 1,4 PPW Erase Current 1,4 PPE Erase Suspend PPES CC 1,4 I Current ...

  • Page 25

    C3 Discrete Table 8: DC Voltage Characteristics (Sheet 2.7 V–3 Sym Parameter V 2.7 V–3.6 V CCQ Note Min Input Low V –0.4 IL Voltage Input High V 2.0 IH Voltage Output Low V ...

  • Page 26

    AC Characteristics 7.1 AC Read Characteristics Table 9: Read Operations—8-Mbit Density Density Product Paramete # Sym Note R1 t Read Cycle Time 3,4 AVAV Address 3,4 AVQV Output Delay CE# to Output R3 ...

  • Page 27

    C3 Discrete Table 10: Read Operations—16-Mbit Density Densit y Produ ct Paramet # Sym (ns Read Cycle Time AVAV Address to Output R2 t AVQV Delay R3 t CE# to Output Delay ELQV OE# to ...

  • Page 28

    Table 11: Read Operations—32-Mbit Density Densit y Produc t Paramet # Sym Min (ns Read Cycle Time AVAV Address to Output R2 t AVQV Delay R3 t CE# to Output Delay ELQV R4 t OE# ...

  • Page 29

    C3 Discrete Table 12: Read Operations — 64-Mbit Density # Sym Parameter R1 t Read Cycle Time AVAV R2 t Address to Output Delay AVQV R3 t CE# to Output Delay ELQV R4 t OE# to Output Delay GLQV R5 ...

  • Page 30

    AC Write Characteristics Table 13: Write Operations—8-Mbit Density # Sym Parameter t / PHWL W1 RP# High Recovery to WE# (CE#) Going Low t PHEL t / ELWL W2 CE# (WE#) Setup to WE# (CE#) Going Low t WLEL ...

  • Page 31

    C3 Discrete Table 14: Write Operations—16-Mbit Density # Sym Parameter t / RP# High Recovery to WE# (CE#) Going PHWL W1 t Low PHEL t / ELWL W2 CE# (WE#) Setup to WE# (CE#) Going Low t WLEL t / ...

  • Page 32

    Table 15: Write Operations—32-Mbit Density # Sym Parameter t / RP# High Recovery to WE# (CE#) PHWL W1 t Going Low PHEL t / CE# (WE#) Setup to WE# (CE#) ELWL W2 t Going Low WLEL t WLWH W3 / ...

  • Page 33

    C3 Discrete Table 16: Write Operations—64-Mbit Density # Symbol RP# High Recovery to WE# (CE#) Going Low PHWL PHEL CE# (WE#) Setup to WE# (CE#) Going Low ELWL WLEL ...

  • Page 34

    Erase and Program Timings Table 17: Erase and Program Timings Symbol Parameter 4-KW Parameter Block t BWPB Word Program Time 32-KW Main Block t BWMB Word Program Time Word Program Time for 0.13 and 0.18 Micron Product t / ...

  • Page 35

    C3 Discrete Figure 12: Transient Equivalent Testing Load Circuit Note: See Table 17 for component values. Table 18: Test Configuration Component Values for Worst-Case Speed Conditions Test Configuration V Min Standard Test CCQ Note: C includes jig capacitance. L 7.5 ...

  • Page 36

    ... The Automatic Power Savings (APS) feature reduces power consumption when the device is selected but idle. If CE# is deasserted, the flash enters its standby mode, where current consumption is even lower. If RP# is deasserted, the flash enter deep power-down mode for ultra-low current consumption. ...

  • Page 37

    ... RP# Connected to System Reset The use of RP# during system reset is important with automated program/erase devices since the system reads from the flash memory when it comes out of reset CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. ...

  • Page 38

    ... Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each V frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads ...

  • Page 39

    ... Read When performing a read cycle, CE# and OE# must be asserted; WE# and RP# must be deasserted. CE# is the device selection control; when active low, it enables the flash memory device. OE# is the data output control; when low, data is output on DQ[15:0]. See Figure 9, “Read Operation Waveform” on page 9 ...

  • Page 40

    ... PLRH As with any automated device important to assert RP# during a system reset. When the system comes out of reset, the processor reads from the flash memory. Automated flash memories provide status information when read during Program or Block-Erase operations CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Numonyx™ ...

  • Page 41

    ... Modes of Operation 10.1 Read Mode The flash memory has four read modes (read array, read identifier, read status, and CFI query) and two write modes (program and erase). Three additional modes (erase suspend to program, erase suspend to read, and program suspend to read) are available only during suspended operations ...

  • Page 42

    ... See 10.1.3 CFI Query The CFI query mode outputs Common Flash Interface (CFI) data after issuing the Read Query Command (0x98). The CFI data structure contains information such as block size, density, command set, and electrical specifications. Once in this mode, read cycles from addresses shown in information ...

  • Page 43

    ... You cna apply VPP during Program and Erase operations for a March 2008 290645-24 Table 25, “Status Register Bit Definition” on page was not within acceptable limits, and the WSM did not execute PP min = 1.65 V. That is Figure 16 on page 52 shows examples of how the flash power PP 47. must remain above PP Datasheet 43 ...

  • Page 44

    ... The only other valid commands while program is suspended are Read Status Register, Read Identifier, CFI Query, and Program Resume. After the Program Resume command is issued to the flash memory, the WSM will continue with the programming process and SR[2] and SR[7] will automatically be cleared. The device automatically outputs Status Register data when read (see Figure 18, “ ...

  • Page 45

    C3 Discrete A Read Array or Program command can now be issued to the CUI to read/program data from/to blocks other than that which is suspended. This nested Program command can subsequently be suspended to read yet another location. The ...

  • Page 46

    ... WSM to execute the Program 40 Program Set-Up algorithm. The flash outputs Status Register data when CE# or OE# is toggled. A Read Array command is required after programming to read array data. See Mode” on page 43 This is a two-cycle command. It prepares the CUI for the Erase Confirm command. If the next command is not an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 to “ ...

  • Page 47

    C3 Discrete Table 25: Status Register Bit Definition WSMS ESS 7 6 SR[7] WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR[6] = ERASE-SUSPEND STATUS (ESS Erase Suspended 0 = Erase In Progress/Completed SR[5] = ...

  • Page 48

    Security Modes 11.1 Flexible Block Locking The C3 Discrete device offers an instant, individual block-locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. This locking scheme offers two ...

  • Page 49

    C3 Discrete The following paragraph concisely summarizes the locking functionality. 11.1.1.1 Locked State The default state of all blocks upon power-up or reset is locked (states [001] or [101]). Locked blocks are fully protected from alteration. Any Program or Erase ...

  • Page 50

    ... The C3 device architecture includes a 128-bit protection register than can be used to increase the security of a system design. For example, the number contained in the protection register can be used to “match” the flash component with other system components, such as the CPU or ASIC, preventing device substitution. Application note, AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture, contains additional application information ...

  • Page 51

    ... When V below or equal to V prompting the corresponding Status Register bit (SR[3 set. March 2008 290645-24 61. Attempting to program to a previously 64-bit Segment (User-Programmable) 128-Bit Protection Register 0 64-bit Segment (Intel Factory-Programmed) PR Lock Register ...

  • Page 52

    ... V Supply 12 V Fast Programming Absolute Write Protection With V System Supply 12 V Supply Low Voltage and 12 V Fast Programming Note resistor can be used if the V CC Advanced+ Boot Block Flash Memory Architecture for details. Datasheet 52 System Supply V CC Prot ≤ KΩ (Logic Signal) Low-Voltage Programming ≤ ...

  • Page 53

    C3 Discrete Appendix A Write State Machine States Table 26 and Table 27 on incoming commands. Table 26: Write State Machine States (Sheet Data Read SR. Current State When Array 7 Read (FFH) Read Read Array “1” ...

  • Page 54

    Table 26: Write State Machine States (Sheet Erase Cmd. Read “1” Status Error Array Erase (Not “0” Status Done) Erase Ers. Susp. Sus. “1” Status Status Read Array Erase Erase Susp. Sus. “1” Array Array Read Array ...

  • Page 55

    C3 Discrete Table 27: Write State Machine States, Continued Prog. Susp. Prog. Susp. Prog. Susp. Read Array Read Config. Read Query Prog. Susp. Prog. Susp. Prog. Susp. Read Config. Read Config. Read Query Prog. Susp. Prog. Susp. Prog. Susp. Read ...

  • Page 56

    Appendix B Flow Charts Figure 17: Word Program Flowchart Start Write 0x40, (Setup) Word Address Write Data, (Confirm) Word Address Read Status Register 0 SR[7] = Suspend? 1 Full Status Check (if desired) Program Complete Read Status Register V 1 ...

  • Page 57

    C3 Discrete Figure 18: Program Suspend / Resume Flowchart PROGRAM SUSPEND / RESUME PROCEDURE Start Write 0xB0 (Program Suspend) Any Address Write 0x70 (Read Status) Any Address Read Status Register 0 SR[ SR[ Write 0xFF ...

  • Page 58

    Figure 19: Erase Suspend / Resume Flowchart Start Write 0xB0, Any Address Write 0x70, Any Address Read Status Register SR[ SR[ Write 0xFF Read Array (Read Array) Data Done Reading 1 Write 0xD0, (Erase Resume) Any ...

  • Page 59

    C3 Discrete Figure 20: Block Erase Flowchart Start Write 0x20, (Block Erase) Block Address Write 0xD0, (Erase Confirm) Block Address Read Status Register Suspend 0 SR[7] = Erase 1 Full Erase Status Check (if desired) Block Erase Complete FULL ERASE ...

  • Page 60

    Figure 21: Locking Operations Flowchart Start Write 0x60, (Lock Setup) Block Address Write either (Lock Confirm) 0x01/0xD0/0x2F, Block Address Write 0x90 (Read Device ID) Read Block Lock Status Locking No Change? Yes Write 0xFF (Read Array) Any Address Lock Change ...

  • Page 61

    C3 Discrete Figure 22: Protection Register Programming Flowchart PROTECTION REGISTER PROGRAMMING PROCEDURE Start Write 0xC0, (Program Setup) PR Address Write PR (Confirm Data) Address & Data Read Status Register 0 SR[ Full Status Check (if desired) Program Complete ...

  • Page 62

    ... Appendix C Common Flash Interface This appendix defines the data structure or “database” returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software detects which command sets to use to enable flash writes, block erases, and otherwise control the flash component ...

  • Page 63

    ... C.3 Block Status Register The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. See Block Erase Status (BSR[1]) allows system software to determine the success of the last block erase operation. BSR[1] can be used just after power-up to verify that the VCC supply was not accidentally removed during an erase operation ...

  • Page 64

    ... BA = Block Address beginning location (i.e., 0x08000 is block 1’s beginning location when the block size is 32K-word). C.4 CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s). See Table 32: CFI Identification Offset ...

  • Page 65

    ... Length 0x27 1 “n” such that device size = 2 0x28 2 Flash device interface: 0x2A 2 “n” such that maximum number of bytes in write buffer = 2 Number of erase block regions within device means no erase blocking; the device erases in “bulk” specifies the number of device or partition regions ...

  • Page 66

    ... C.6 Numonyx-Specific Extended Query Table Certain flash features and commands are optional as shown in Vendor Specific Extended Query” on page table specifies these features as well as other similar types of information. Table 36: Primary-Vendor Specific Extended Query (Sheet Offset Length P = 0x15 (Optional Flash Features and Commands) ...

  • Page 67

    ... Notes: 1. The variable pointer which is defined at CFI offset 0x15. Table 37: Protection Register Information 1 Offset Length P = 0x35 (Optional Flash Features and Commands) Number of Protection register fields in JEDEC ID space. 0x(P+E) 1 “00h,” indicates that 256 protection bytes are available 0x(P+F) 0x(P+10) (0xP+11) Protection Field 1: Protection Description This field describes user-available One Time Programmable (OTP) Protection register bytes ...

  • Page 68

    ... Order Number 297938 3 Volt Advanced+ Boot Block Flash Memory Specification Update 292216 AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory 292215 AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture Contact your Numonyx Numonyx™ Flash Data Integrator (Numonyx™ FDI) Software Developer’s Kit ...

  • Page 69

    ... GT = 48- Ball µBGA * CSP BGA CSP RC = Easy BGA Free Easy BGA Free VFBGA Free TSOP Product line designator ® for all Intel Flash products Device Density 640 = x16 (64 Mbit) 320 = x16 (32 Mbit) 160 = x16 (16 Mbit) 800 = x16 (8 Mbit) March 2008 290645-24 ...

  • Page 70

    ... All other assembly codes without an “E” or “S” as the first character are production units. Datasheet 70 48-Ball µBGA* CSP 48-Ball VF BGA GE28F320C3TD70 GE28F320C3BD70 GE28F320C3TC70 GE28F320C3BC70 GT28F320C3TA100 GE28F320C3TC90 GT28F320C3BA100 GE28F320C3BC90 ...