GE28F320C3BD70 Intel, GE28F320C3BD70 Datasheet - Page 37

• Manufacturer Part Number: GE28F320C3BD70
• Manufacturer: Intel

Specifications of GE28F320C3BD70

• Density: 32Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 2M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

C3 Discrete
8.5
8.5.1
8.5.2
8.5.3
8.5.4
Table 20: Reset Specifications
March 2008
290645-24
t
PLPH
Symbol
RP# Low to Reset during Read
(If RP# is tied to V
applicable)
Power and Reset Considerations
Power-Up/Down Characteristics
To prevent any condition that may result in a spurious write or erase operation,
Numonyx recommends to power-up VCC and VCCQ together. Conversely, VCC and
VCCQ must power-down together.
Numonyx also recommends that you power-up VPP with or after VCC has reached
VCC
If VCCQ and/or VPP are not connected to the VCC supply, then VCC must attain VCC
before applying VCCQ and VPP. Device inputs must not be driven before supply voltage
reaches VCC
Power supply transitions must only occur when RP# is low.
RP# Connected to System Reset
The use of RP# during system reset is important with automated program/erase
devices since the system reads from the flash memory when it comes out of reset. If a
CPU reset occurs without a flash memory reset, proper CPU initialization will not occur
because the flash memory may be providing status information instead of array data.
Numonyx recommends connecting RP# to the system CPU RESET# signal to allow
proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when V
V
signal to V
protection since alteration of memory contents can only occur after successful
completion of the two-step command sequences. The device is also disabled until RP#
is brought to V
reset during power-up/down, invalid bus conditions during power-up can be masked,
providing yet another level of memory protection.
V
The CUI latches commands as issued by system software and is not altered by V
CE# transitions or WSM actions. Its default state upon power-up, after exit from reset
mode or after V
After any program or Block-Erase operation is complete (even after V
down to V
if access to the flash-memory array is desired.
Reset Specifications
LKO
CC
min
. Because both WE# and CE# must be low for a command write, driving either
, V
. Conversely, VPP must powerdown with or slightly before VCC.
PP
PPLK
IH
and RP# Transitions
CC
min
will inhibit writes to the device. The CUI architecture provides additional
Parameter
), the CUI must be reset to read-array mode by the Read Array command
, this specification is not
IH
.
CC
, regardless of the state of its control inputs. By holding the device in
transitions above V
LKO
(Lockout voltage), is read-array mode.
Min
100
V
CC
2.7 V – 3.6 V
Max
CC
voltages are above
Unit
ns
PP
transitions
Notes
Datasheet
1, 2
PP
or
min
37