GE28F320C3BD70 Intel, GE28F320C3BD70 Datasheet - Page 9

• Manufacturer Part Number: GE28F320C3BD70
• Manufacturer: Intel

Specifications of GE28F320C3BD70

• Density: 32Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 2M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

C3 Discrete
2.0
2.1
March 2008
290645-24
Functional Overview
This section provides an overview of the Numonyx™ Advanced+ Boot Block Flash
Memory (C3) device features and architecture.
Product Overview
The C3 flash memory device provides high-performance asynchronous reads in
package-compatible densities with a 16 bit data bus. Individually-erasable memory
blocks are optimally sized for code and data storage. Eight 4 Kword parameter blocks
are located in the boot block at either the top or bottom of the device’s memory map.
The rest of the memory array is grouped into 32 Kword main blocks.
The device supports read-array mode operations at various I/O voltages (1.8 V and 3
V) and erase and program operations at 3 V or 12 V VPP. With the 3 V I/O option, VCC
and VPP can be tied together for a simple, ultra-low-power design. In addition to I/O
voltage flexibility, the dedicated VPP input provides complete data protection when V
≤ V
The C3 Discrete device features a 128-bit protection register enabling security
techniques and data protection schemes through a combination of factory-programmed
and user-programmable OTP data registers. Zero-latency locking/unlocking on any
memory block provides instant and complete protection for critical system code and
data. Additional block lock-down capability provides hardware protection where
software commands alone cannot change the block’s protection status.
A command User Interface (CUI) serves as the interface between the system processor
and internal operation of the device. A valid command sequence issued to the CUI
initiates device automation. An internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for block erase, program, and lock-bit
configuration operations.
The device offers three low-power saving features: Automatic Power Savings (APS),
standby mode, and deep power-down mode. The device automatically enters APS
mode following read cycle completion. Standby mode begins when the system
deselects the flash memory by deasserting Chip Enable, CE#. The deep power-down
mode begins when Reset Deep Power-Down, RP# is asserted, which deselects the
memory and places the outputs in a high-impedance state, producing ultra-low power
savings. Combined, these three power-savings features significantly enhanced power
consumption flexibility.
PPLK
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Datasheet
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