MC68HC11E0CFN3 Freescale Semiconductor, MC68HC11E0CFN3 Datasheet - Page 98
MC68HC11E0CFN3
Manufacturer Part Number
MC68HC11E0CFN3
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC11E0CFN3.pdf
(242 pages)
Specifications of MC68HC11E0CFN3
Cpu Family
HC11
Device Core Size
8b
Frequency (max)
3MHz
Interface Type
SCI/SPI
Program Memory Type
ROMLess
Program Memory Size
Not Required
Total Internal Ram Size
512Byte
# I/os (max)
38
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
52
Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC11E0CFN3
Manufacturer:
MOT
Quantity:
119
Company:
Part Number:
MC68HC11E0CFN3R2
Manufacturer:
FREESCALE
Quantity:
1 831
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6.2 Port A
Port A shares functions with the timer system and has:
DDRA7 — Data Direction for Port A Bit 7
PAEN — Pulse Accumulator System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
PEDGE — Pulse Accumulator Edge Control Bit
DDRA3 — Data Direction for Port A Bit 3
I4/O5 — Input Capture 4/Output Compare 5 Bit
RTR[1:0] — RTI Interrupt Rate Select Bits
98
Parallel Input/Output (I/O) Ports
•
•
•
Overridden if an output compare function is configured to control the PA7 pin
The pulse accumulator uses port A bit 7 as the PAI input, but the pin can also be used as
general-purpose I/O or as an output compare.
Refer to
Refer to
Refer to
This bit is overridden if an output compare function is configured to control the PA3 pin.
Refer to
Refer to
0 = Input
1 = Output
0 = Input
1 = Output
Three input-only pins
Three output-only pins
Two bidirectional I/O pins
Alternate function:
Chapter 9 Timing
Chapter 9 Timing
Chapter 9 Timing
Chapter 9 Timing
Chapter 9 Timing
Even when port A bit 7 is configured as an output, the pin still drives the
input to the pulse accumulator.
Address:
Address:
And/or:
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 6-2. Pulse Accumulator Control Register (PACTL)
I = Indeterminate after reset
DDRA7
$1000
$1026
OC1
Bit 7
PA7
Bit 7
PAI
0
I
Systems.
Systems.
Systems.
Systems.
Systems.
Figure 6-1. Port A Data Register (PORTA)
PAEWN
M68HC11E Family Data Sheet, Rev. 5.1
OC2
OC1
PA6
6
0
6
0
PAMOD
OC3
OC1
PA5
5
0
5
0
NOTE
PEDGE
OC4
OC1
PA4
4
0
4
0
IC4/OC5
DDRA3
OC1
PA3
3
3
0
I
I4/O5
PA2
IC1
—
2
2
0
I
RTR1
PA1
IC2
—
1
1
0
I
Freescale Semiconductor
RTR0
Bit 0
PA0
Bit 0
IC3
—
0
I
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