LM3S308 Luminary Micro, Inc, LM3S308 Datasheet - Page 28
LM3S308
Manufacturer Part Number
LM3S308
Description
Lm3s308 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S308.pdf
(419 pages)
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Architectural Overview
1.4.4.1
1.4.4.2
1.4.4.3
28
UART (see page 256)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S308 controller includes two fully programmable 16C550-type UARTs that support data
transfer speeds up to 1.5625 Mbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.)
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
SSI (see page 295)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S308 controller includes one SSI module that provides the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
I
The Inter-Integrated Circuit (I
(a serial data line SDA and a serial clock line SCL).
The I
devices, LCDs, tone generators, and so on. The I
diagnostic purposes in product development and manufacture.
The LM3S308 controller includes one I
IC devices over an I
and read) data.
Devices on the I
both sending and receiving data as either a master or a slave, and also supports the simultaneous
operation as both a master and a slave. The four I
Slave Transmit, and Slave Receive.
A Stellaris
Both the I
a transmit or receive operation completes (or aborts due to an error). The I
interrupts when data has been sent or requested by a master.
2
C (see page 332)
2
C bus interfaces to external I
2
®
C master and slave can generate interrupts. The I
I
2
C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
2
C bus can be designated as either a master or a slave. The I
2
C bus. The I
2
C) bus provides bi-directional data transfer through a two-wire design
2
2
C bus supports devices that can both transmit and receive (write
C devices such as serial memory (RAMs and ROMs), networking
Preliminary
2
C module that provides the ability to communicate to other
2
2
C bus may also be used for system testing and
C modes are: Master Transmit, Master Receive,
2
C master generates interrupts when
2
C slave generates
2
C module supports
June 04, 2008
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