st10f272z2 STMicroelectronics, st10f272z2 Datasheet - Page 108

• Manufacturer Part Number: st10f272z2
• Description: 16-bit Mcu With 256 Kbyte Flash Memory And 20 Kbyte Ram
• Manufacturer: STMicroelectronics

Power reduction modes
Note:
21.2.1
21.2.2
21.3
108/189
Before entering Power Down mode (by executing the instruction PWRDN), bit VREGOFF in
XMISC register must be set.
Leaving the main voltage regulator active during Power Down may lead to unexpected
behavior (ex: CPU wake-up) and power consumption higher than what specified.
Protected power down mode
This mode is selected when PWDCFG (bit 5) of SYSCON register is cleared. The Protected
Power Down mode is only activated if the NMI pin is pulled low when executing PWRDN
instruction (this means that the PWRD instruction belongs to the NMI software routine). This
mode is only deactivated with an external hardware reset on RSTIN pin.
Interruptible power down mode
This mode is selected when PWDCFG (bit 5) of SYSCON register is set.
The Interruptible Power Down mode is only activated if all the enabled Fast External
Interrupt pins are in their inactive level.
This mode is deactivated with an external reset applied to RSTIN pin or with an interrupt
request applied to one of the Fast External Interrupt pins, or with an interrupt generated by
the Real-Time Clock, or with an interrupt generated by the activity on CAN’s and I
interfaces. To allow the internal PLL and clock to stabilize, the RSTIN pin must be held low
according the recommendations described in
An external RC circuit must be connected to RPD pin, as shown in the
Figure 36. External RC circuitry on RPD pin
To exit Power Down mode with an external interrupt, an EXxIN (x = 7...0) pin has to be
asserted for at least 40 ns.
Stand-by mode
In Stand-by mode, it is possible to turn off the main V
through the dedicated pin of the ST10F272Z2.
To enter Stand-by mode it is mandatory to held the device under reset: once the device is
under reset, the RAM is disabled (see XRAM2EN bit of XPERCON register), and its digital
interface is frozen in order to avoid any kind of data corruption.
A dedicated embedded low-power voltage regulator is implemented to generate the internal
low voltage supply (about 1.65 V in Stand-by mode) to bias all those circuits that shall
remain active: the portion of XRAM, the RTC counters and 32 kHz on-chip oscillator
amplifier.
ST10F272
RPD
Chapter 20: System reset on page
+
V
DD
R0
C0
220kΩ minimum
1µF Typical
DD
provided that V
Figure
STBY
is available
36.
ST10F272Z2
2
81.
C module