st10f272z2 STMicroelectronics, st10f272z2 Datasheet - Page 94

• Manufacturer Part Number: st10f272z2
• Description: 16-bit Mcu With 256 Kbyte Flash Memory And 20 Kbyte Ram
• Manufacturer: STMicroelectronics

System reset
20.5
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Refer to next Figures
29
Watchdog timer reset
When the watchdog timer is not disabled during the initialization, or serviced regularly
during program execution, it will overflow and trigger the reset sequence.
Unlike hardware and software resets, the watchdog reset completes a running external bus
cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after
the programmed wait states.
When READY is sampled inactive (high) after the programmed wait states the running
external bus cycle is aborted. Then the internal reset sequence is started.
Bit P0.12...P0.8 are latched at the end of the reset sequence and bit P0.7...P0.2 are cleared
(that is written at ‘1’).
A Watchdog reset is always taken as synchronous: there is no influence on Watchdog Reset
behavior with RPD status. In case Bidirectional Reset is selected, a Watchdog Reset event
pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled
low even though Bidirectional Reset is selected.
Refer to next Figures
29
Figure 25. SW / WDT unidirectional RESET (EA = 1)
for bidirectional.
for bidirectional.
RSTIN
P0[15:13]
P0[12:8]
P0[7:2]
P0[1:0]
IBUS-CS
(Internal)
FLARST
RST
RSTOUT
25
25
and
and
26
26
for unidirectional SW reset timing, and to Figures 27,
for unidirectional SW reset timing, and to Figures 27,
1024 TCL
not transparent
not transparent
not transparent
transparent
≤ 1 ms
≤ 2 TCL
not t.
not t.
7 TCL
ST10F272Z2
28
28
and
and