st10f272z2 STMicroelectronics, st10f272z2 Datasheet - Page 180

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st10f272z2

Manufacturer Part Number
st10f272z2
Description
16-bit Mcu With 256 Kbyte Flash Memory And 20 Kbyte Ram
Manufacturer
STMicroelectronics
Datasheet

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Electrical characteristics
25.8.19
180/189
External bus arbitration
V
Table 82.
1. Partially tested, guaranteed by design characterization.
Figure 62. External bus arbitration (releasing the bus)
1. The ST10F272Z2 will complete the currently running bus cycle before granting bus access.
2. This is the first possibility for BREQ to become active.
3. The CS outputs will be resistive high (pull-up) after t
t
t
t
t
t
t
t
61
62
63
64
65
66
67
DD
Symbol
= 5 V ± 10%, V
SR
CC
CC
CC
CC
CC
CC
CLKOUT
HOLD
HLDA
BREQ
CSx
(P6.x)
Others
External bus arbitration timings
HOLD input setup time
to CLKOUT
CLKOUT to HLDA high
or BREQ low delay
CLKOUT to HLDA low
or BREQ high delay
CSx release
CSx drive
Other signals release
Other signals drive
SS
Parameter
= 0 V, T
t
1)
61
A
= -40 to +125 °C, C
1)
1)
1)
min.
18.5
– 4
– 4
F
TCL = 12.5 ns
CPU
64
.
= 40 MHz
t
66
t
63
L
= 50 pF
max.
12.5
12.5
20
15
20
15
t
t
62
64
3)
2)
1/2 TCL = 1 to 64 MHz
Variable CPU Clock
min.
18.5
– 4
– 4
max.
12.5
12.5
20
15
20
15
ST10F272Z2
ns
ns
ns
ns
ns
ns
ns

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