st10f272z2 STMicroelectronics, st10f272z2 Datasheet - Page 183

• Manufacturer Part Number: st10f272z2
• Description: 16-bit Mcu With 256 Kbyte Flash Memory And 20 Kbyte Ram
• Manufacturer: STMicroelectronics

ST10F272Z2
25.8.20.2 Slave mode
Table 84.
t
t
t
t
t
t
t
t
t
310
311
312
313
314
315
316
317p
318p
Symbol
CC Write data valid after shift edge
CC Write data hold after shift edge
SR SSC clock cycle time
SR SSC clock high time
SR SSC clock low time
SR SSC clock rise time
SR SSC clock fall time
SR
SR
SSC slave mode timings
Figure 64. SSC master timing
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
2. The bit timing is repeated for all bits to be transmitted or received.
V
Read data setup time before latch
edge, phase error detection on
(SSCPEN = 1)
Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
DD
SCLK
MTSR
MRST
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
= 5 V ±10%, V
Parameter
1)
t
305
SS
(2)
t
1st in bit
307
= 0 V, T
1st out bit
t
300
t
308
A
t
= -40 to +125 °C, C
305
t
301
t
304
(<SSCBR> = 0002h)
min.
2nd out bit
150
@f
63
63
62
87
Max. Baudrate
–
–
–
0
2nd In bit
t
302
6.6 MBd
CPU
= 40 MHz
t
303
(1)
t
306
max.
150
)
10
10
55
–
–
–
–
–
L
= 50 pF
2)
t
t
4TCL + 12
6TCL + 12
310
310
(<SSCBR> = 0001h -
t
8TCL
305
min.
Variable Baudrate
/ 2 – 12
/ 2 – 12
–
–
0
–
t
Electrical characteristics
Last in bit
307
Last out bit
FFFFh)
t
308
262144 TCL
2TCL + 30
max.
10
10
–
–
–
–
–
183/189
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns