st10f272z2 STMicroelectronics, st10f272z2 Datasheet - Page 155

• Manufacturer Part Number: st10f272z2
• Description: 16-bit Mcu With 256 Kbyte Flash Memory And 20 Kbyte Ram
• Manufacturer: STMicroelectronics

ST10F272Z2
25.8
25.8.1
25.8.2
AC characteristics
Test waveforms
Figure 46. Input / output waveforms
Figure 47. Float waveforms
Definition of internal timing
The internal operation of the ST10F272Z2 is controlled by the internal CPU clock f
edges of the CPU clock can trigger internal (for example pipeline) or external (for example
bus cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the time
between two consecutive edges of the CPU clock, called “TCL”.
The CPU clock signal can be generated by different mechanisms. The duration of TCL and
its variation (and also the derived external timing) depends on the mechanism used to
generate f
This influence must be regarded when calculating the timings for the ST10F272Z2.
The example for PLL operation shown in
The mechanism used to generate the CPU clock is selected during reset by the logic levels
on pins P0.15-13 (P0H.7-5).
0.4V
2.4V
V
LOAD
For timing purposes a port pin is no longer floating when V
It begins to float when a 100mV change from the loaded V
CPU
AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’.
Timing measurements are made at V
V
V
.
LOAD
LOAD
+ 0.1V
- 0.1V
2.0V
0.8V
Test Points
Figure 48
Reference
Timing
Points
V
IH
V
OL
OH
min. for a logic ‘1’ and V
2.0V
0.8V
refers to a PLL factor of 4.
OH
LOAD
/V
Electrical characteristics
OL
changes of ±100mV.
level occurs (I
IL
max for a logic ‘0’.
V
V
OL
OH
+ 0.1V
- 0.1V
OH
CPU
/I
OL
155/189
. Both
= 20m