st10f272z2 STMicroelectronics, st10f272z2 Datasheet - Page 81

• Manufacturer Part Number: st10f272z2
• Description: 16-bit Mcu With 256 Kbyte Flash Memory And 20 Kbyte Ram
• Manufacturer: STMicroelectronics

ST10F272Z2
20
20.1
System reset
System reset initializes the MCU in a predefined state. There are six ways to activate a reset
state. The system start-up configuration is different for each case as shown in
Table 49.
1)
2)
3)
Input filter
On RSTIN input pin an on-chip RC filter is implemented. It is sized to filter all the spikes
shorter than 50ns. On the other side, a valid pulse shall be longer than 500ns to grant that
ST10 recognizes a reset command. In between 50ns and 500ns a pulse can either be
filtered or recognized as valid, depending on the operating conditions and process
variations.
For this reason all minimum durations mentioned in this Chapter for the different kind of
reset events shall be carefully evaluated taking into account of the above requirements.
In particular, for Short Hardware Reset, where only 4 TCL is specified as minimum input
reset pulse duration, the operating frequency is a key factor. Examples:
●
●
Power-on reset
Asynchronous Hardware reset
Synchronous Long Hardware
reset
Synchronous Short Hardware
reset
Watchdog Timer reset
Software reset
RSTIN pulse should be longer than 500ns (Filter) and than settling time for configuration of Port0.
See next
The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD
low inhibits the Bidirectional reset on SW and WDT reset events, that is RSTIN is not activated (refer to
Sections 20.4,
For a CPU clock of 64 MHz, 4 TCL is 31.25 ns, so it would be filtered. In this case the
minimum becomes the one imposed by the filter (that is 500 ns).
For a CPU clock of 4 MHz, 4 TCL is 500 ns. In this case the minimum from the formula
is coherent with the limit imposed by the filter.
Reset Source
Section 20.1
Reset event definition
20.5
and 20.6).
for more details on minimum reset pulse duration.
SHWR
WDTR
PONR
LHWR
SWR
Flag
Status
RPD
High
High
Low
Low
3)
3)
Power-on
t
t
500ns)
t
t
500ns)
WDT overflow
SRST instruction execution
RSTIN
RSTIN
RSTIN
RSTIN
>
> max(4 TCL, 500ns)
> (1032 + 12) TCL + max(4 TCL,
≤ (1032 + 12) TCL + max(4 TCL,
1)
Conditions
System reset
Table
49.
81/189