st10f272z2 STMicroelectronics, st10f272z2 Datasheet - Page 56

• Manufacturer Part Number: st10f272z2
• Description: 16-bit Mcu With 256 Kbyte Flash Memory And 20 Kbyte Ram
• Manufacturer: STMicroelectronics

Interrupt system
9.1
56/189
Table 29.
Hardware traps are exceptions or error conditions that arise during run-time. They cause
immediate non-maskable system reaction similar to a standard interrupt service (branching
to a dedicated vector table location).
The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any other program execution. Hardware trap services cannot not
be interrupted by standard interrupt or by PEC interrupts.
X-Peripheral interrupt
The limited number of X-Bus interrupt lines of the present ST10 architecture, imposes some
constraints on the implementation of the new functionality. In particular, the additional X-
Peripherals SSC1, ASC1, I
and PEC transfer capabilities. For this reason, a multiplexed structure for the interrupt
management is proposed. In the next
diagram, which shows the basic structure replicated for each of the four X-interrupt available
vectors (XP0INT, XP1INT, XP2INT and XP3INT).
It is based on a set of 16-bit registers XIRxSEL (x=0,1,2,3), divided in two portions each:
●
●
When different sources submit an interrupt request, the enable bits (Byte High of XIRxSEL
register) define a mask which controls which sources will be associated with the unique
GPT2 Timer 6
GPT2 CAPREL Register
A/D Conversion Complete
A/D Overrun Error
ASC0 Transmit
ASC0 Transmit Buffer
ASC0 Receive
ASC0 Error
SSC Transmit
SSC Receive
SSC Error
PWM Channel 0...3
See Paragraph
See Paragraph
See Paragraph
See Paragraph
Source of Interrupt or
PEC Service Request
Byte High
Byte Low
Interrupt sources (continued)
9.1
9.1
9.1
9.1
2
C, PWM1 and RTC need some resources to implement interrupt
Request
S0TBIR
PWMIR
ADCIR
ADEIR
SCRIR
SCEIR
S0RIR
SCTIR
S0TIR
S0EIR
XP0IR
XP1IR
XP2IR
XP3IR
CRIR
T6IR
Flag
XIRxSEL[15:8]
XIRxSEL[7:0]
Figure
S0TBIE
PWMIE
Enable
SCRIE
ADCIE
ADEIE
SCEIE
S0RIE
S0EIE
SCTIE
XP0IE
XP1IE
XP2IE
XP3IE
S0TIE
CRIE
T6IE
Flag
9, the principle is explained through a simple
Interrupt Enable bits
Interrupt Flag bits
Interrupt
S0TBINT
PWMINT
ADCINT
ADEINT
SCRINT
SCEINT
S0RINT
SCTINT
S0TINT
S0EINT
XP0INT
XP1INT
XP2INT
XP3INT
Vector
CRINT
T6INT
00’00BCh
00’009Ch
00’011Ch
00’00ACh
00’00FCh
00’010Ch
Location
00’00A0h
00’00A4h
00’00A8h
00’00B0h
00’00B4h
00’00B8h
00’0098h
00’0100h
00’0104h
00’0108h
Vector
ST10F272Z2
Number
Trap
2Ch
2Ah
2Bh
2Dh
2Eh
2Fh
3Fh
26h
27h
28h
29h
47h
40h
41h
42h
43h