st10f272z2 STMicroelectronics, st10f272z2 Datasheet - Page 157

• Manufacturer Part Number: st10f272z2
• Description: 16-bit Mcu With 256 Kbyte Flash Memory And 20 Kbyte Ram
• Manufacturer: STMicroelectronics

ST10F272Z2
25.8.4
25.8.5
25.8.6
Prescaler operation
When pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the
internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of f
the duration of an individual TCL) is defined by the period of the input clock f
The timings listed in the AC Characteristics that refer to TCL therefore can be calculated
using the period of f
Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set,
then the PLL is switched off.
Direct drive
When pins P0.15-13 (P0H.7-5) equal ’011’ during reset the on-chip phase locked loop is
disabled, the on-chip oscillator amplifier is bypassed and the CPU clock is directly driven by
the input clock signal on XTAL1 pin.
The frequency of CPU clock (f
low time of f
input clock f
Therefore, the timings given in this chapter refer to the minimum TCL. This minimum value
can be calculated by the following formula:
For two consecutive TCLs, the deviation caused by the duty cycle of f
so the duration of 2TCL is always 1/f
The minimum value TCL
of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula:
The address float timings in Multiplexed bus mode (t
TCL (TCL
Similarly to what happen for Prescaler Operation, if the bit OWDDIS in SYSCON register is
cleared, the PLL runs on its free-running frequency and delivers the clock signal for the
Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.
Oscillator watchdog (OWD)
An on-chip watchdog oscillator is implemented in the ST10F272Z2. This feature is used for
safety operation with external crystal oscillator (available only when using direct drive mode
with or without prescaler, so the PLL is not used to generate the CPU clock multiplying the
frequency of the external crystal oscillator). This watchdog oscillator operates as following.
The reset default configuration enables the watchdog oscillator. It can be disabled by setting
the OWDDIS (bit 4) of SYSCON register.
When the OWD is enabled, the PLL runs at its free-running frequency, and it increments the
watchdog counter. On each transition of external clock, the watchdog counter is cleared. If
max
XTAL
CPU
= 1/f
.
(i.e. the duration of an individual TCL) is defined by the duty cycle of the
CPU
XTAL
XTAL
is half the frequency of f
x DC
min
for any TCL.
has to be used only once for timings that require an odd number
max
CPU
TCL min
) instead of TCL
) directly follows the frequency of f
DC
XTAL
2TCL
=
=
.
1 f ⁄
duty cycle
=
XTALl
1 f XTAL
⁄
XTAL
min
xlDC min
.
11
and the high and low time of f
and t
45
) use the maximum duration of
Electrical characteristics
XTAL
XTAL
so the high and
is compensated,
XTAL
.
CPU
157/189
(i.e.