st10f272z2 STMicroelectronics, st10f272z2 Datasheet - Page 134

• Manufacturer Part Number: st10f272z2
• Description: 16-bit Mcu With 256 Kbyte Flash Memory And 20 Kbyte Ram
• Manufacturer: STMicroelectronics

Known limitations
24.5
24.6
Note:
134/189
Flash wake-up from idle mode
Description
When waking up from idle mode, the Flash response time is slower than in running mode.
This can lead to an incorrect data read or code fetch when the CPU frequency is greater
than 55 MHz.
As a consequence, the use of IDLE instruction is not allowed for frequencies higher than
55 MHz.
Workaround
There is no workaround for frequencies higher than 55 MHz.
Executing PWRDN instruction
Description
The Power-down mode is not entered and the PWRDN instruction is ignored in the following
cases:
●
●
However, under the conditions described below, the PWRDN instruction is not ignored, and
no further instructions are fetched from external memory, that is, the CPU is in a quasi-idle
state.
This problem only occurs in the following situations:
1.
2.
The on-chip peripherals still work correctly, in particular the watchdog timer. if the watchdog
timer is not disabled, it resets the device upon an overflow. However, interrupts and PEC
transfers cannot be processed. If NMI is asserted low while the device is in this quasi-idle
state, power down mode is entered.
No problem occurs if the NMI pin is low (if PWDCFG = 0) or if all Port 2 pins used to exit
from power down mode are at inactive level (if PWDCFG = 1): the chip enters normally
power down mode.
Workaround
Ensure that no instruction that writes to external memory or to an XPeripheral precedes the
PWRDN instruction. Otherwise, insert a NOP instruction in front of PWRDN. When a
The PWRDN instruction is executed while NMI is high (PWDCFG bit of the SYSCON
register cleared)
The PWRDN instruction is executed while at least one of the Port 2 pins used to exit
from Power-down mode (PWDCFG bit of the SYSCON register is set) is at the active
level.
The instructions following the PWRDN instruction are located in an external memory
and a multiplexed bus configuration with memory tristate waitstate (bit MTTCx = 0)
is used.
The instruction preceding the PWRDN instruction writes to external memory or an
XPeripheral (such as XRAM or CAN) and the instructions following the PWRDN
instruction are located in external memory. In this case, the problem occurs for any bus
configuration.
ST10F272Z2