isp1760 NXP Semiconductors, isp1760 Datasheet - Page 17

• Manufacturer Part Number: isp1760
• Description: Hi-speed Universal Serial Bus Host Controller For Embedded Applications
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13257
Product data sheet
7.3.1 PIO mode access—memory read cycle
7.3.2 PIO mode access—memory write cycle
register access must always be completed using two subsequent accesses. In the case of
a DMA transfer, the 16-bit or 32-bit data bus width configuration will determine the number
of bursts that will complete a certain transfer length.
In PIO mode, CS_N, WR_N and RD_N are used to access registers and memory. In DMA
mode, the data validation is performed by DACK—instead of CS_N—together with the
WR_N and RD_N signals. The DREQ signal will always be asserted as soon as the
ISP1760 DMA is enabled, as described in the following section.
The following method has been implemented to reduce the read access timing in the case
of a memory read:
The PIO memory write access is similar to a normal memory access. It is not necessary
to set the prefetching address before a write cycle to the memory.
The ISP1760 internal write address will not be automatically incremented during
consecutive write accesses, unlike in a series of ISP1760 memory read cycles. The
memory write address must be incremented before every access.
•
•
•
The Memory register contains the starting address and the bank selection to read
from the memory. Before every new read cycle of the same or different banks, an
appropriate value is written to this register.
Once a value is written to this register, the address is stored in the FIFO of that bank
and is then used to prefetch data for the memory read of that bank.
For every subsequent read operation executed at a contiguous address, the address
pointer corresponding to that bank is automatically incremented to prefetch the next
data to be sent to the CPU.
Memory read accesses for multiple banks can be interleaved. In this case, the FIFO
block handles the MUXing of appropriate data to the CPU.
The address written to the Memory register is incremented and used to successively
prefetch data from the memory irrespective of the value on the address bus for each
bank, until a new value for a bank is written to the Memory register.
For example, consider the following sequence of operations:
– Write the starting (read) address 4000h and bank1 = 01 to the Memory register.
– Write the starting (read) address 4100h and bank2 = 10 to the Memory register.
When RD_N is asserted for three cycles with A[17:16] = 01, the returned data
corresponds to addresses 4000h, 4004h and 4008h.
Remark: Once 4000h is written to the Memory register for bank1, the bank select
value determines the successive incremental addresses used to fetch the data.
That is, the fetching of data is independent of the address on A[15:0] lines.
When RD_N is asserted for four cycles with A[17:16] = 10, the returned data
corresponds to addresses 4100h, 4104h, 4108h and 410Ch.
Consequently, the RD_N assertion with A[17:16] = 01 will return data from 400Ch
because the bank1 read stopped there in the previous cycle. Also, RD_N
assertions with A[17:16] = 010 will now return data from 4110h because the bank2
read stopped there in the previous cycle.
Rev. 01 — 8 November 2004
Embedded Hi-Speed USB host controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1760
17 of 105