isp1760 NXP Semiconductors, isp1760 Datasheet - Page 20

• Manufacturer Part Number: isp1760
• Description: Hi-speed Universal Serial Bus Host Controller For Embedded Applications
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13257
Product data sheet
Additional IRQ characteristics can be adjusted in the Edge Interrupt Count register, as
necessary, applicable only when IRQ is set to be edge-active (a pulse of a defined width is
generated every time IRQ is active).
Bits 15 to 0 of the Edge Interrupt Count register define the IRQ pulse width. The maximum
pulse width that can be programmed is FFFFh, corresponding to a 1 ms pulse width. This
setting is necessary for certain processors that may require a different minimum IRQ
pulse width than the default value. The default IRQ pulse width set at power on is
approximately 500 ns.
Bits 31 to 24 of the Edge Interrupt Count register define the minimum interval between
two interrupts to avoid frequent interrupts to the CPU. The default value of 00h attributed
to these bits determines the normal IRQ generation, without any delay. When a delay is
programmed and the IRQ becomes active after the respective delay, several IRQ events
may have already occurred.
All the interrupt events are represented by the respective bits allocated in the Interrupt
register. There is no mechanism to show the order or the moment of occurrence of an
interrupt.
The asserted bits in the Interrupt register can be cleared by writing back the same value to
the Interrupt register. This means that writing logic 1 to each of the set bits will reset the
corresponding bits to the initial inactive state.
The IRQ generation rules that apply according to the preceding settings are:
The IRQ generation can also be conditioned by programming the IRQ Mask OR and
IRQ Mask AND registers. Setting some of the bits in these registers to logic 1 will
determine the IRQ generation only when the respective AND or OR conditions of
completing the respective PTDs is met.
3. Define the IRQ polarity as active LOW or active HIGH in INTR_POL (bit 2) of the HW
4. Program the individual interrupt enable bits in the Interrupt Enable register. The
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Mode Control register. These settings must match the IRQ settings of the host
processor.
By default, interrupt is level-triggered and active LOW.
software will need to clear the interrupt status bits in the Interrupt register before
enabling individual interrupt enable bits.
If an event of interrupt occurs but the respective bit in the Interrupt Enable register is
not set, then the respective Interrupt register bit is set but the interrupt signal is not
asserted.
An interrupt will be generated when interrupt is enabled and the respective bit in the
Interrupt Enable register is set.
For a level trigger, an interrupt signal remains asserted until the processor clears the
Interrupt register by writing logic 1 to clear the Interrupt register bits that are set.
If an interrupt is made edge-sensitive and is asserted, writing to clear the Interrupt
register will not have any effect because the interrupt will be asserted for a prescribed
amount of clock cycles.
The clock stopping mechanism does not affect the generation of an interrupt. This is
useful during the suspend and resume cycles, when an interrupt is generated to
signal a wake-up event.
Rev. 01 — 8 November 2004
Embedded Hi-Speed USB host controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1760
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