isp1760 NXP Semiconductors, isp1760 Datasheet - Page 55

• Manufacturer Part Number: isp1760
• Description: Hi-speed Universal Serial Bus Host Controller For Embedded Applications
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9. Philips Transfer Descriptor
9397 750 13257
Product data sheet
Table 63:
The standard EHCI data structures as described in Enhanced Host Controller Interface
Specification for Universal Serial Bus Rev. 1.0 are optimized for the bus master operation
that is managed by the hardware state machine.
The PTD structures of the ISP1760 are translations of the EHCI data structures that are
optimized for the ISP1760, while keeping the architecture of the EHCI data structures the
same. This is because the ISP1760 is a slave Host Controller and has no bus master
capability.
EHCI manages schedules in two lists: periodic and asynchronous. The data structures
are designed to provide the maximum flexibility required by USB, minimize memory traffic,
and hardware and software complexity. The ISP1760 controller executes transactions for
devices by using a simple shared-memory schedule. This schedule consists of data
structures organized into three lists.
qISO — Isochronous transfer
qINTL — Interrupt transfer
qATL — Asynchronous transfer; for the control and bulk transfers.
The system software maintains two lists for the Host Controller: periodic and
asynchronous. The root of the periodic schedule—the PERIODICLISTBASE register—is
the physical memory base address of the periodic frame list. The periodic frame list is an
array memory pointer. The objects referenced from the frame list must be valid schedule
data structures. The asynchronous list base is also a common list of queue heads
(endpoints) that are served in a schedule. These endpoint data structures are further
linked to the EHCI transfer descriptor that is the valid schedule (queue PTD).
The Periodic Schedule Enable (ISO_BUF_FULL and INT_BUF_FULL) or Asynchronous
Schedule Enable (ATL_BUF_FULL) bits can enable traversal to these lists. Enabling a list
indicates the presence of valid schedule in the list. The system software starts at these
points, schedules the first transfer inside the shared memory of the ISP1760, and sets up
the ATL, INTL or ITL bit corresponding to the type of transfer scheduled in the shared
memory.
The ISP1760 has a maximum of 32 ISO, 32 INTL and 32 ATL PTDs. These PTDs are
used as channels to transfer data from the shared memory to the USB bus. These
channels are allocated and deallocated on receiving the transfer from the core USB driver.
Bit
31 to 0 ATL_IRQ_
Symbol
MASK_
AND[31:0]
ATL IRQ Mask AND register: bit description
Access Value
R/W
Rev. 01 — 8 November 2004
0000 0000h ATL IRQ Mask AND: Represents a direct map for
Description
ATL PTDs 31 to 0.
0 — No OR condition defined between ATL PTDs
1 — The bits corresponding to certain PTDs are set
to logic 1 to define a certain AND condition between
the 32 ATL PTDs.
Embedded Hi-Speed USB host controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1760
55 of 105