FWIXEPAD0SE001 INTEL [Intel Corporation], FWIXEPAD0SE001 Datasheet
FWIXEPAD0SE001
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FWIXEPAD0SE001 Summary of contents
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Intel LXT9785 and Intel Advanced 8-Port 10/100 Mbps PHY Transceivers ® ® The Intel LXT9785 and Intel LXT9785E are 8-port Fast Ethernet PHY Transceivers supporting IEEE 802.3 physical layer applications at 10 Mbps and 100 Mbps. These devices provide ...
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY ...
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Contents 1.0 Introduction.................................................................................................................................. 18 1.1 What You Will Find in This Document ................................................................................ 18 1.2 Related Documents ............................................................................................................ 18 2.0 Block Diagram ............................................................................................................................. 19 3.0 Pin/Ball Assignments and Signal Descriptions ........................................................................ 20 3.1 PQFP Pin Assignments ...................................................................................................... 20 3.1.1 PQFP ...
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Contents 4.3.7 MDIO Management Interface .............................................................................. 121 4.3.8 MII Sectionalization.............................................................................................. 123 4.3.9 MII Interrupts........................................................................................................ 123 4.3.10 Global Hardware Control Interface ...................................................................... 124 4.3.11 FIFO Initial Fill Values.......................................................................................... 124 4.4 Operating Requirements................................................................................................... 125 4.4.1 Power Requirements ........................................................................................... 125 4.4.2 Clock/SYNC Requirements ...
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Network Operations .........................................................................145 4.9.2 100BASE-X Protocol Sublayer Operations..........................................................145 4.9.2.1 PCS Sublayer ......................................................................................145 4.9.3 PMA Sublayer ......................................................................................................147 4.9.3.1 Link ......................................................................................................148 4.9.3.2 Link Failure Override............................................................................148 4.9.3.3 Carrier Sense/Data Valid (RMII) ..........................................................148 4.9.3.4 Carrier Sense (SMII) ............................................................................148 4.9.3.5 Receive Data Valid ...
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Contents 5.2.5 The Fiber Interface .............................................................................................. 166 5.2.6 LED Circuit........................................................................................................... 167 5.3 Typical Application Circuits............................................................................................... 168 6.0 Test Specifications.................................................................................................................... 173 7.0 Register Definitions................................................................................................................... 199 8.0 Package Specifications............................................................................................................. 221 9.0 Ordering Information................................................................................................................. 227 Figures ® 1 Intel LXT9785/LXT9785E Block Diagram ................................................................................. ...
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Intel LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing.............................................178 ® 40 Intel LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing............................................179 ® 41 Intel LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing.............................................180 ® 42 Intel LXT9785/LXT9785E SMII - 100BASE-FX Transmit Timing............................................181 ® 43 Intel LXT9785/LXT9785E ...
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Contents 18 Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Signal Name ...... 52 19 Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Ball Location ...... 57 20 Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric ...
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Intel LXT9785/LXT9785E SS-SMII - 100BASE-TX Transmit Timing......................................185 ® 68 Intel LXT9785/LXT9785E SS-SMII - 100BASE-FX Receive Timing Parameters ...................186 ® 69 Intel LXT9785/LXT9785E SS-SMII - 100BASE-FX Transmit Timing Parameters ..................187 ® 70 Intel LXT9785/LXT9785E SS-SMII - 10BASE-T Receive Timing ...
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Contents Revision History Page Description 21 Modified Figure 2 “Intel® LXT9785 and Intel® LXT9785E RMII 208-Pin PQFP 22 Modified Table 2 “Intel® LXT9785/LXT9785E RMII PQFP Pin 26 Modified Figure 3 “Intel® LXT9785/LXT9785E SMII 208-Pin PQFP 27 Modified Table 3 “Intel® ...
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Page Description 120 Modified/added text under 121 Modified text under Section 4.3.7, “MDIO Management 121 Added note under second paragraph. Added last paragraph. 123 Added note under 124 Added new Section 4.3.11, “FIFO Initial Fill Values” 125 Modified paragraph three ...
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Contents Page Description 162 Added Section 4.14, “Link Hold-Off 173 Modified Table 52 “Intel® LXT9785/LXT9785E Operating Conditions” 176 Modified Table 58 “Intel® LXT9785/LXT9785E 100BASE-FX Transceiver Characteristics” Added note to 178- Parameters” 195 Parameters”. Added table note to 178 Parameters”. Added ...
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Page Description Changed "pseudo-ECL (PECL)" to "Low Voltage Positive Emitter Coupled Logic (LVPECL)" in the 1 second paragraph, front page. Modified Table 5 “Intel® LXT9785/LXT9785E RMII Signal Descriptions – 36 sentence to RXER0 through RXER7 signal description. 42 Modified Table ...
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Contents Page Description 200 Modified Table 83 “Control Register (Address 201 Modified Table 84 “Status Register (Address 204 Modified Table 87 “Auto-Negotiation Advertisement Register (Address 205 Modified Table 88 “Auto-Negotiation Link Partner Base Page Ability Register (Address 207 Modified Table ...
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Page Description 146 Modified Table 69 “Port Configuration Register (Address 16, Hex 10)” (Bits 16.5 and 16.6) 148 Modified Table 71 “Interrupt Enable Register (Address 18, Hex 12)” 168 Added product ordering table and diagram. Page Description 1 Modified and ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 1.0 Introduction This document contains information on the Intel 10/100 Mbps Fast Ethernet transceivers. 1.1 What You Will Find in This Document This document contains the following sections: • Section 3.0, ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 2.0 Block Diagram Figure 1 provides the LXT9785/LXT9785E block diagram. ® Figure 1. Intel LXT9785/LXT9785E Block Diagram RMII/SMII Contr ADD_<4:0> Management / Mode Select MDIO 2 Logic & LED MDC Drivers ...
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Intel LXT9785 and Intel LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.0 Pin/Ball Assignments and Signal Descriptions 3.1 PQFP Pin Assignments The following sections show PQFP pin assignments and signal descriptions: • Section 3.1.1, “PQFP Pin Assignments – ...
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Intel LXT9785 and Intel 3.1.1 PQFP Pin Assignments – RMII Configuration Figure 2 and Table 2, “Intel® LXT9785/LXT9785E RMII PQFP Pin List” on page 22 LXT9785/LXT9785 RMII PQFP pin assignments. ® Figure 2. Intel LXT9785 and Intel CRS_DV6.......1 RxER6/LINKHOLD..2 ...
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Intel LXT9785 and Intel LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 2. Intel LXT9785/LXT9785E RMII PQFP Pin List Pin Symbol 1 CRS_DV6 RxER6/ 2 LINKHOLD 3 TxEN6 4 TxData6_0 5 TxData6_1 6 REFCLK1 7 RxData5_1 8 ...
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Intel LXT9785 and Intel Pin Symbol RxER0/ 59 MDIX 60 TxEN0 61 TxData0_0 62 TxData0_1 63 MDC0 64 MDIO0 65 VCCD 66 GNDD 67 MDINT0 68 LED3_3 69 LED3_2 70 LED3_1 71 LED2_3 72 LED2_2 73 LED2_1 74 GNDIO ...
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Intel LXT9785 and Intel LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Pin Symbol 125 TPFOP3 126 GNDR3 127 GNDT2/3 128 TPFIN3 129 TPFIP3 130 VCCR3 131 VCCR4 132 TPFIP4 133 TPFIN4 134 GNDT4/5 135 GNDR4 136 TPFOP4 137 ...
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Intel LXT9785 and Intel Pin Symbol 194 LED7_3 195 GNDD 196 VCCD 197 RxData7_1 198 RxData7_0 199 GNDIO 200 CRS_DV7 201 RxER7 202 TxEN7 203 TxData7_0 204 TxData7_1 205 RxData6_1 206 RxData6_0 207 GNDIO 208 VCCIO Datasheet Document Number: ...
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Intel LXT9785 and Intel LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.1.2 PQFP Pin Assignments – SMII Configuration Figure 3 and Table 3, “Intel® LXT9785/LXT9785E SMII PQFP Pin List” on page 27 LXT9785/LXT9785E SMII PQFP pin assignments. ® ...
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Intel LXT9785 and Intel ® Table 3. Intel LXT9785/LXT9785E SMII PQFP Pin List Pin Symbol 1 N/C N/C 2 (LINKHOLD) 3 N/C 4 TxData6 5 N/C 6 REFCLK1 7 N/C 8 RxData5 9 GNDIO 10 N/C 11 FIFOSEL1 12 ...
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Intel LXT9785 and Intel LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Pin Symbol 68 LED3_3 69 LED3_2 70 LED3_1 71 LED2_3 72 LED2_2 73 LED2_1 74 GNDIO 75 LED1_3 76 LED1_2 77 LED1_1 78 VCCD 79 GNDD 80 ...
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Intel LXT9785 and Intel Pin Symbol 130 VCCR3 131 VCCR4 132 TPFIP4 133 TPFIN4 134 GNDT4/5 135 GNDR4 136 TPFOP4 137 TPFON4 138 VCCT4/5 139 TPFON5 140 TPFOP5 141 GNDR5 142 TPFIN5 143 TPFIP5 144 VCCR5 145 VCCR6 146 ...
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Intel LXT9785 and Intel LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Pin Symbol 193 LED7_2 194 LED7_3 195 GNDD 196 VCCD 197 N/C 198 RxData7 199 GNDIO 200 N/C 201 N/C 202 N/C 203 TxData7 204 SYNC1 205 ...
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Intel LXT9785 and Intel 3.1.3 PQFP Pin Assignments – SS-SMII Configuration Figure 4 and Table 4, “Intel® LXT9785/LXT9785 SS-SMII PQFP Pin List” on page 32 the LXT9785/LXT9785E SS-SMII PQFP pin assignments. ® Figure 4. Intel LXT9785/LXT9785E SS-SMII 208-Pin PQFP ...
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Intel LXT9785 and Intel LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 4. Intel LXT9785/LXT9785 SS-SMII PQFP Pin List Pin Symbol 1 N/C N/C 2 LINKHOLD 3 N/C 4 TxData6 5 N/C 6 REFCLK1 7 RxData5 8 ...
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Intel LXT9785 and Intel Pin Symbol 67 MDINT0 68 LED3_3 69 LED3_2 70 LED3_1 71 LED2_3 72 LED2_2 73 LED2_1 74 GNDIO 75 LED1_3 76 LED1_2 77 LED1_1 78 VCCD 79 GNDD 80 LED0_3 81 LED0_2 82 LED0_1 83 ...
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Intel LXT9785 and Intel LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Pin Symbol 135 GNDR4 136 TPFOP4 137 TPFON4 138 VCCT4/5 139 TPFON5 140 TPFOP5 141 GNDR5 142 TPFIN5 143 TPFIP5 144 VCCR5 145 VCCR6 146 TPFIP6 147 ...
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Intel LXT9785 and Intel Pin Symbol 203 TxData7 204 TxSYNC1 205 RxData6 206 N/C 207 GNDIO 208 VCCIO Datasheet Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 ® LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Reference ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.2 PQFP Signal Descriptions 3.2.1 Signal Name Conventions Signal names may contain either a port designation or a serial designation combination of the two designations. Signal naming conventions are ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 5. Intel LXT9785/LXT9785E RMII Signal Descriptions – PQFP (Sheet Pin-Ball Designation PQFP PBGA 34 D8 A11, 23 C10 13 B13, 14 D11 4 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 5. Intel LXT9785/LXT9785E RMII Signal Descriptions – PQFP (Sheet Pin-Ball Designation PQFP PBGA 206 C15, 205 B17 198 E16, 197 F14 58 E4, 49 C4, 39 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 6. Intel LXT9785/LXT9785E SMII / SS-SMII Common Signal Descriptions – PQFP Pin/Ball Designation PQFP PBGA 61 E2, 52 C3, 42 B5, 34 D8, 22 A11, 13 B13, 4 D13, ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 8. Intel LXT9785/LXT9785E SS-SMII Specific Signal Descriptions – PQFP Pin/Ball Designation PQFP PBGA 35 A6, 204 C16 58 E4, 17 B12 32 C8, 201 D17 60 E3, 21 B11 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 9. Intel LXT9785/LXT9785E MDIO Control Interface Signals – PQFP Pin/Ball Designation PQFP PBGA 64 F3, 25 A10 67 F1 E1, 24 B10 Type ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 10. Intel LXT9785/LXT9785E Signal Detect – PQFP Pin/Ball Designation PQFP PBGA P2, 97 N4, 100 P3, 101 N5, 161 P15, 162 P16, 165 P17, 166 N17 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 12. Intel LXT9785/LXT9785E JTAG Test Signal Descriptions – PQFP Pin/Ball Designation PQFP PBGA 167 N14 168 N15 169 N16 170 M16 171 M17 1. Type Column Coding ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 13. Intel LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP (Sheet Pin/Ball Designation PQFP PBGA 50 D5 174 L14 175 M15 88 L4, 89 M2, 90 M3, 91 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 13. Intel LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP (Sheet Pin/Ball Designation PQFP PBGA L2 173 M14 1. ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 13. Intel LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP (Sheet Pin/Ball Designation PQFP PBGA 11 A15 20 A12 A17 1. Type Column Coding: I ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 14. Intel LXT9785/LXT9785E LED Signal Descriptions – PQFP (Sheet Pin/Ball Designation PQFP PBGA 82 K3 J4 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 14. Intel LXT9785/LXT9785E LED Signal Descriptions – PQFP (Sheet Pin/Ball Designation PQFP PBGA 185 J15, 186 J16, 187 H17 189 H15, 190 H16, 191 G17 192 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 15. Intel LXT9785/LXT9785E Power Supply Signal Descriptions – PQFP (Sheet Pin/Ball Designation PQFP PBGA N6, N7, 109, 123, N9, N11, 138, 152 N12 A1, A9, B3, ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 16. Intel LXT9785/LXT9785E Unused/Reserved Pins – PQFP Pin/Ball Designation PQFP PBGA F15, G2, G5, G14, G16, H4, N/C H14, J2, J13, K4, K15 1. Type Column Coding ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.3 BGA23 Ball Assignments The following sections provide BGA23 ball location and signal description information for RMII, SMII, and SS-SMII: • Table 3.3.1 “RMII BGA23 Ball List” on page 52 • ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.3.1 RMII BGA23 Ball List The following tables provide the RMII BGA23 ball locations and signal names arranged in alphanumeric order as follows: • Table 18 “Intel® LXT9785/LXT9785E RMII BGA23 Ball ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type GNDT P14 – GNDT R1 GNDT R3 GNDT R5 GNDT R15 – GNDT R17 – GNDT T17 – GNDT U2 GNDT U4 GNDT U6 GNDT U10 – GNDT ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type No ball F6 No ball F7 No ball F8 No Ball E8 No Ball E10 No Ball F9 No Ball F10 – No Ball F11 – No Ball ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type RxER5 A15 (FIFOSEL1) RxER6LINK A17 HOLD RxER7 D17 SD_2P5V P1 SD0 P2 SD1 N4 SD2 P3 SD3 N5 SD4 P15 I SD5 P16 I SD6 P17 I SD7 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type TxEN7 D16 I, ID TxSLEW_0 N3 TxSLEW_1 M4 VCCD F5 VCCD G13 – VCCD J5 VCCD J14 – VCCIO A2 VCCIO A8 VCCIO C1 VCCIO C11 – VCCIO ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 19. Intel® LXT9785/LXT9785E RMII BGA23 Ball List in Alphanumeric Order by Ball Location Ball Signal A1 GNDD A2 VCCIO A3 RxData1_0 A4 TxData2_1 A5 CRS_DV2 A6 TxData3_1 A7 TxEN3 A8 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal D16 TxEN7 D17 RxER7 E1 MDC0 E2 TxData0_0 E3 TxEN0 E4 CRS_DV0 E5 GNDD E6 REFCLK0 E7 GNDD E8 No Ball E9 GNDD E10 No Ball E11 GNDD E12 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal H15 LED6_1 H16 LED6_2 H17 LED5_3 J1 LED0_3 J2 N/C J3 LED1_2 J4 LED1_1 J5 VCCD J6 No Ball J7 No Ball J8 GNDD J9 GNDD J10 GNDD J11 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal M15 RESET M16 TCK M17 TRST N1 ADD_1 N2 ADD_0 N3 TxSLEW_0 N4 SD1 N5 SD3 N6 VCCT N7 VCCT N8 No Ball N9 VCCT N10 No Ball N11 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal U6 GNDT U7 TPFOP3 U8 GNDR U9 TPFIN4 U10 GNDT U11 TPFON5 U12 GNDT U13 TPFIP5 U14 GNDT U15 TPFON6 U16 GNDT U17 GNDT Datasheet Document Number: 249241 Revision ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.3.2 SMII BGA23 Ball List The following tables provide the SMII ball locations and signal names arranged in alphanumeric order as follows: • Table 20 “Intel® LXT9785/LXT9785E SMII BGA23 Ball List ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type GNDR R11 – GNDR R13 – GNDR U8 – GNDT P14 – GNDT R1 – GNDT R3 – GNDT R5 – GNDT R15 – GNDT R17 – GNDT ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type N/C B1 N/C B2 N/C B4 N/C B9 N/C B11 I, ID N/C B15 O, TS, ID N/C B17 O, TS, ID N/C C6 N/C C7 N/C C8 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type No Ball M11 – No Ball M12 – No Ball N8 – No Ball N10 – O, TS, SL, PAUSE D5 ID TS, SL, PREASEL ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type TxData7 E14 I, ID TxSLEW_0 N3 TxSLEW_1 M4 VCCD F5 VCCD G13 – VCCD J5 VCCD J14 – VCCIO A2 VCCIO A8 VCCIO C1 VCCIO C11 – VCCIO ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 21. Intel® LXT9785/LXT9785E SMII BGA23 Ball List in Alphanumeric Order by Ball Location Ball Signal Type A1 GNDD – A2 VCCIO – A3 RxData1 N ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Type D16 N TS, SL, D17 N MDC0 I, ST TxData0 N CRS_DV0 O, TS, SL ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Type OD, TS, SL, H15 LED6_1 IP OD, TS, SL, H16 LED6_2 IP OD, TS, SL, H17 LED5_3 IP OD, TS, SL, J1 LED0_3 IP J2 N/C – OD, ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Type M15 RESET I, ST, IP M16 TCK I, ST, ID M17 TRST I, ST ADD_1 I, ST ADD_0 I, ST TxSLEW_0 I, ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Type U6 GNDT – U7 TPFOP3 AO/AI U8 GNDR – U9 TPFIN4 AO/AI U10 GNDT – U11 TPFON5 AO/AI U12 GNDT – U13 TPFIP5 AO/AI U14 GNDT – U15 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.3.3 SS-SMII BGA23 Ball List The following tables provide the SS-SMII ball locations and signal names arranged in alphanumeric order as follows: • Table 22 “Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type GNDR P6 AO/AI GNDR P13 AO/AI GNDR R7 AO/AI GNDR R9 AO/AI GNDR R11 AO/AI GNDR R13 AO/AI GNDR U8 – GNDT P14 AO/AI GNDT R1 AO/AI GNDT ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type N/C C15 – N/C D4 – N/C D9 – N/C D11 – N/C D16 – OD, TS, N/C E16 SL, IP OD, TS, N/C F4 SL, IP OD, ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type PREASEL PWRDWN L14 – OD, TS, REFCLK0 E6 SL, IP OD, TS, REFCLK1 E12 SL, IP RESET M15 O, TS, ID RxCLK0 E3 – RxData0 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Type TxSYNC0 A6 I, ST, IP TxSYNC1 C16 – OD, TS, VCCD F5 SL, IP VCCD G13 I, ID VCCD J5 – VCCD J14 – VCCIO A2 I, ST, ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 23. Intel® LXT9785/LXT9785E SS-SMII BGA23 Ball List in Alphanumeric Order by Ball Location Ball Symbol Type A1 GNDD – A2 VCCIO – ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Symbol Type D16 N TS, SL, D17 TxCLK1 ID E1 MDC0 I, ST TxData0 RxCLK0 CRS_DV0 O, TS, SL ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Symbol Type OD, TS, H15 LED6_1 SL, IP OD, TS, H16 LED6_2 SL, IP OD, TS, H17 LED5_3 SL, IP OD, TS, J1 LED0_3 SL N/C – OD, ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Symbol Type M15 RESET I, ST, IP M16 TCK I, ST, ID M17 TRST I, ST ADD_1 I, ST ADD_0 I, ST TxSLEW_0 I, ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Symbol Type U6 GNDT – U7 TPFOP3 AO/AI U8 GNDR – U9 TPFIN4 AO/AI U10 GNDT – U11 TPFON5 AO/AI U12 GNDT – U13 TPFIP5 AO/AI U14 GNDT – U15 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.4 BGA23 Signal Descriptions 3.4.1 Signal Name Conventions Signal names may contain either a port designation or a serial designation combination of the two designations. Signal naming conventions are ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 24. Intel LXT9785/LXT9785E RMII Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP D8 A11, 22 C10 23 B13, 13 D11 14 D13, ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 24. Intel LXT9785/LXT9785E RMII Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP C15, 206 B17 205 E16, 198 F14 197 E4, 58 C4, 49 A5, ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 25. Intel LXT9785/LXT9785E SMII / SS-SMII Common Signal Descriptions – BGA23 Ball/Pin Designation BGA23 PQFP E2, 61 C3, 52 B5, 42 D8, 34 A11, 22 B13, 13 D13, 4 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 27. Intel LXT9785/LXT9785E SS-SMII Specific Signal Descriptions – BGA23 Ball/Pin Designation BGA23 PQFP A6, 35 C16 204 E4, 58 B12 17 C8, 32 D17 201 E3, 60 B11 21 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 28. Intel LXT9785/LXT9785E MDIO Control Interface Signals – BGA23 Ball/Pin Designation BGA23 PQFP F3, 64 A10 25 F1 E1, 63 B10 Type ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 29. Intel LXT9785/LXT9785E Signal Detect – BGA23 Ball/Pin Designation BGA23 PQFP P1 95 P2, 96 N4, 97 P3, 100 N5, 101 P15, 161 P16, 162 P17, 165 N17 166 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 31. Intel LXT9785/LXT9785E JTAG Test Signal Descriptions – BGA23 Ball/Pin Designation BGA23 PQFP N14 167 N15 168 N16 169 M16 170 M17 171 1. Type Column Coding ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 32. Intel LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP N3 L14 174 M15 175 1. Type Column ...
Page 89
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 32. Intel LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP L4, 88 M2, 89 M3 L17, 178 L16 ...
Page 90
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 32. Intel LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP D2 59 L2 M14 173 1. Type Column ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 32. Intel LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP A15 11 A12 A17 2 1. Type Column Coding: I ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 33. Intel LXT9785/LXT9785E LED Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP K3 J4 H2, ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 33. Intel LXT9785/LXT9785E LED Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP J15, 185 J16, 186 H17 187 H15, 189 H16, 190 G17 191 G15, ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 34. Intel LXT9785/LXT9785E Power Supply Signal Descriptions – BGA23 (Sheet Ball/Pin Designation BGA23 PQFP N6, N7, 109, 123, N9, N11, 138, 152 N12 A1, A9, B3, ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 35. Intel LXT9785/LXT9785E Unused/Reserved Pins – BGA23 Pin/Ball Designation BGA23 PQFP F15, G2, G5, G14, G16, H4, N/C H14, J2, J13, K4, K15 1. Type Column Coding ...
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Intel LXT9785 and Intel LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.5 BGA15 Ball Assignments The following figure and tables provide the BGA15 ball locations and signal names arranged in alphanumeric order as follows: • Figure 6 “Intel® ...
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Intel LXT9785 and Intel 3.5.1 BGA15 Ball List The following tables provide the RMII BGA23 ball locations and signal names arranged in alphanumeric order as follows: Table 37 “Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Signal Name” ...
Page 98
Intel LXT9785 and Intel LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Name GNDD J6 GNDD J7 GNDD J8 GNDD K5 GNDD K6 GNDD K9 GNDD K10 GNDD L2 GNDD N1 GNDD N11 GNDD P1 GNDD P11 ...
Page 99
Intel LXT9785 and Intel Signal Ball Name N/C L10 N/C M4 N/C M5 N/C M6 N/C M7 N/C M8 N/C P2 N/C P3 REFCLK0 L4 REFCLK1 C3 RESET C10 RXCLK G1 RxData0_S N3 RxData0_SS M3 RxData1_S M2 RxData1_SS M1 ...
Page 100
Intel LXT9785 and Intel LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Signal Ball Name TRST A10 TXCLK J3 TxData0 N4 TxData1 N2 TxData2 K3 TxData3 J1 TxData4 G3 TxData5 E2 TxData6 D3 TxData7 A5 TXSLEW_0 M11 TXSLEW_1 M12 ...
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Intel LXT9785 and Intel Table 38 shows the ball locations and signal names arranged in order by ball location. Table 38. Intel® LXT9785MBC BGA15 Ball List in Alphanumeric Order by Ball Location (SMII/ SS-SMII) Ball Signal Name A1 GNDD ...
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Intel LXT9785 and Intel LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Name C14 TPIP6 D1 N/C D2 N/C D3 TxData6 D4 VCCIO D5 N/C D6 N/C D7 VCCD D8 N/C D9 GNDD D10 N/C D11 GNDD ...
Page 103
Intel LXT9785 and Intel Ball Signal Name G6 GNDD G7 GNDD G8 GNDD G9 AVSS G10 AVSS G11 AVSS G12 AVCC G13 TPIN4 G14 TPIP4 H1 N/C H2 RxData3_SS H3 RxData3_S H4 VCCIO H5 N/C H6 GNDD H7 GNDD ...
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Intel LXT9785 and Intel LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Ball Signal Name K12 AVCC K13 TPOP2 K14 TPON2 L1 N/C L2 GNDD L3 VCCIO L4 REFCLK0 L5 VCCIO L6 N/C L7 VCCD L8 N/C L9 CFG_2 ...
Page 105
Intel LXT9785 and Intel Ball Signal Name P2 N/C P3 N/C P4 MDC P5 MDINT P6 LED3_1 P7 LED2_1 P8 LED1_2 P9 LED0_2 P10 ADD_3 P11 GNDD P12 TPIP0 P13 TPOP0 P14 TPON1 Datasheet Document Number: 249241 Revision Number: ...
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Intel LXT9785 and Intel LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 108 Datasheet Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3.6 BGA15 Signal Descriptions 3.6.1 Signal Name Conventions Signal names may contain either a port designation or a serial designation combination of the two designations. Signal naming conventions are ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 39. Intel LXT9785 BGA15 Signal Descriptions (Sheet BGA15 Ball Designation N3, RxData0_S M2, RxData1_S K2, RxData2_S H3, RxData3_S F2, RxData4_S E3, RxData5_S B4, RxData6_S C5 RxData7_S ...
Page 109
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 39. Intel LXT9785 BGA15 Signal Descriptions (Sheet BGA15 Ball Designation P4 P13, N13, TPOP0, TPON0 N14, P14, TPOP1, TPON1 K13, K14, TPOP2, TPON2 J14, J13, TPOP3, ...
Page 110
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 39. Intel LXT9785 BGA15 Signal Descriptions (Sheet BGA15 Ball Designation TxSLEW_0 M11, M12 TxSLEW_1 C10 N10, P10 E8 MODESEL_1 C9, MODESEL_0 1. Type Column Coding: I ...
Page 111
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 39. Intel LXT9785 BGA15 Signal Descriptions (Sheet BGA15 Ball Designation K8 M10, L9 Type Column Coding Input, ...
Page 112
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 39. Intel LXT9785 BGA15 Signal Descriptions (Sheet BGA15 Ball Designation N8, P8 P7, N7, P6, N6 B9, A9 B8, A8 A7, B7 B6, A6 D12, E12, ...
Page 113
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 39. Intel LXT9785 BGA15 Signal Descriptions (Sheet BGA15 Ball Designation E11, F9, F10, F11, G9, G10, G11, H9, H10, H11, J9, J10, J11, K11, L11 D7, ...
Page 114
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.0 Functional Description 4.1 Introduction ® The Intel LXT9785/LXT9785E is an 8-port Fast Ethernet 10/100 PHY transceiver that supports 10 Mbps and 100 Mbps networks, complying with all applicable requirements of ...
Page 115
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers The OSP-based LXT9785/LXT9785E provides improved data recovery, EMI performance and power consumption. 4.1.2 Comprehensive Functionality The LXT9785/LXT9785E performs all functions of the Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA) ...
Page 116
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 7. Intel LXT9785/LXT9785E Interfaces Data Interface MDIO Management Interface Port LEDs/ Controls Addr & MDIX/ Contr 4.2.1.1 Twisted-Pair Interface The LXT9785/LXT9785E supports either 100BASE-TX or 10BASE-T connections over 100 ...
Page 117
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers During 10 Mbps operation, LXT9785/LXT9785E encoded data is exchanged. When no data are being exchanged, the line is left in an idle state with NLPs transmitted to maintain link. 4.2.1.2 MDI ...
Page 118
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 41. Intel LXT9785/LXT9785E MII Mode Select ModeSel1 1 RMII SMII SS-SMII Reserved 1. Invalid for the BGA15 package. 4.3.2 Internal Loopback Register bit 0.14 must be set to enable ...
Page 119
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.3.4 Serial Media Independent Interface (SMII) and Source Synchronous- Serial Media Independent Interface (SS-SMII) 4.3.4.1 SMII Interface The LXT9785/LXT9785E provides an independent serial interface for each network port, complying with the ...
Page 120
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers. Some registers are required and their functions are defined by the IEEE 802.3 specification. ...
Page 121
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 11. Intel LXT9785/LXT9785E Port Address Scheme 4.3.8 MII Sectionalization When sectionalized into two quad sections, the MDIO bus splits into two separate PHY access ports. Ports 0-3 of the ...
Page 122
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers • Auto-negotiation complete. • Speed status change. • Duplex status change. • Link status change. • Isolate status change. ® Figure 12. Intel LXT9785/LXT9785E Interrupt Logic Event X Enable Reg Event ...
Page 123
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.4 Operating Requirements 4.4.1 Power Requirements The LXT9785/LXT9785E requires four power supply inputs: VCCD, VCCA, VCCPECL and VCCIO. The digital and analog circuits require 2.5 V supplies (VCCD, VCCR, and VCCT). ...
Page 124
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.4.2.5 RxCLK Signal (SS-SMII only) In SS-SMII mode, the LXT9785/LXT9785E provides a 125 MHz clock output in reference to the output RxDatan. RxCLK is referenced and synchronized to the REFCLK. See ...
Page 125
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 13. Intel LXT9785/LXT9785E Initialization Sequence Reset MDIO Registers to Control Interface at last 4.5.3 Power-Down Mode The LXT9785/LXT9785E incorporates numerous features to maintain the lowest power possible. The device ...
Page 126
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Note: Intel recommends that a minimum recovery time be allowed after bringing up a port from software or hardware power-down or link hold-off modes. The recovery times are specified in “Intel® ...
Page 127
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Intel recommends that a minimum recovery time be allowed after bringing up a port from software or hardware reset. The recovery times are specified in Power-Up Timing Parameters” on page 198 ...
Page 128
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.6.1.2 Manual Next Page Exchange Additional information, exceeding that required by base page exchange, is also sent via “Next Pages.” The LXT9785/LXT9785E fully supports the IEEE 802.3 method of negotiation via ...
Page 129
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.6.1.5 Parallel Detection In parallel with auto-negotiation, the LXT9785/LXT9785E also monitors for 10 Mbps Normal Link Pulses (NLP) or 100 Mbps Idle symbols. If either symbol is detected, the device automatically ...
Page 130
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.7 Serial MII Operation The LXT9785/LXT9785E exchanges transmit and receive data with the controller via the Serial MII (SMII). The SMII performs the following functions: • Conveys complete MII information between ...
Page 131
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 15. Intel LXT9785/LXT9785E Typical SMII Interface Diagram 125 MHz Sourced Externally or from Switch ASIC Datasheet Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Typical SMII ...
Page 132
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 16. Intel LXT9785/LXT9785E Typical SMII Quad Sectionalization Diagram 125 MHz Sourced Externally or from Switch ASIC 134 Typical SMII Interface in a 24-Port System RefClk0 RefClk1 8 TxDatan SYNC0 ...
Page 133
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 17. Intel LXT9785/LXT9785E 100 Mbps Serial MII Data Flow Serial Data Stream To/From MAC 4.7.1 SMII Reference Clock The ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 18. Intel LXT9785/LXT9785E Serial MII Transmit Synchronization CLOCK TxSYNC TX TxER TxEN 4.7.4 Receive Data Stream Receive data and control information are signalled in ten-bit segments. In 100 Mbps ...
Page 135
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 19. Intel LXT9785/LXT9785E Serial MII Receive Synchronization CLOCK RxSYNC RX CRS ® Table 44. Intel LXT9785/LXT9785E RX Status Encoding Bit Definitions Signal CRS Carrier Sense - identical to MII, ...
Page 136
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 45. Intel LXT9785/LXT9785E SS-SMII Signal To TxData PHY TxCLK PHY TxSYNC PHY RxData MAC RxCLK MAC RxSYNC MAC REFCLK MAC 138 From Purpose MAC Transmit data & control MAC ...
Page 137
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 20. Intel LXT9785/LXT9785E Typical SS-SMII Interface Diagram 125 MHz Sourced Externally or from Switch ASIC Datasheet Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Typical SS-SMII ...
Page 138
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 21. Intel LXT9785/LXT9785E Typical SS-SMII Quad Sectionalization Diagram 125 MHz Sourced Externally or from Switch ASIC 140 Typical SS-SMII Interface in a 24-Port System RefClk1 RefClk0 8 TxData n ...
Page 139
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 22. Intel LXT9785/LXT9785E SS-SMII Transmit Timing TxCLK TxSYNC TxData TxCLK TxSYNC TxData All signals are synchronous to the clock ® Figure 23. Intel LXT9785/LXT9785E SS-SMII Receive Timing 4.8 RMII ...
Page 140
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.8.2 Transmit Enable TxENn must be asserted and de-asserted synchronously with REFCLK. The MAC must assert TxENn at the same time as the first nibble of preamble. TxENn must be de-asserted ...
Page 141
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 25. Intel LXT9785/LXT9785E Typical RMII Interface Diagram 50 Mhz Sourced Externally or from Switch ASIC Datasheet Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Typical RMII ...
Page 142
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 26. Intel LXT9785/LXT9785E Typical RMII Quad Sectionalization Diagram 50 MHz Sourced Externally or from Switch ASIC 144 Typical RMII Interface in a 24-Port System RefClk0 RefClk1 8 TxD0n 8 ...
Page 143
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.9 100 Mbps Operation 4.9.1 100BASE-X Network Operations During 100BASE-X operation, the LXT9785/LXT9785E transmits and receives 5-bit symbols across the network link. is not actively transmitting data, the LXT9785/LXT9785E sends out ...
Page 144
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.9.2.1.1 Preamble Handling When the MAC asserts TxEN, the PCS substitutes a /J/K/ symbol pair, also known as the Start-of- Stream Delimiter (SSD), for the first two nibbles received across the ...
Page 145
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.9.3 PMA Sublayer The 100BASE-X PMA protocol uses the 4B/5B data encoding scheme to encode/decode the data streams. The coding scheme is shown in Table 46. 4B/5B Coding 4B Code Code ...
Page 146
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.9.3.1 Link In 100 Mbps mode, the LXT9785/LXT9785E establishes a link whenever the descrambler becomes locked and remains locked for approximately 50 ms. Whenever the descrambler loses lock (<12 consecutive idle ...
Page 147
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.9.3.6 Twisted-Pair PMD Sublayer The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and descrambling, line coding and decoding (MLT-3 for 100BASE-TX, Manchester for 10T), as well as receiving, ...
Page 148
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers The far-end fault detection process in fiber operation requires idles to establish link. Link will not establish if a far-end fault pattern is the initial signal detected. Either fault condition causes ...
Page 149
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.10.2 Dribble Bits The LXT9785/LXT9785E device handles dribble bits in all modes. If one through four dribble bits are received, the nibble is passed across the RMII. If five through seven ...
Page 150
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.11 DTE Discovery Process The DTE discovery process is port dependent and must be enabled through software. The process is implemented as a next page option to the auto-negotiation flow. When ...
Page 151
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.11.2 Interaction between Processor, MAC, and PHY The state machines that control the mechanics of the Discovery process reside within the LXT9785E device. However, control of the power supply and overall ...
Page 152
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers DTE DISCOVERY PROCESS ENABLE - Register Bit 27.6 (Dis_EN) R/W Default value = 0: Disabled. Register bit 27.6 controls the operation of the process. The discovery process is disabled when Register ...
Page 153
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers associated with message code #5 (Organizationally Unique Identifier (OUI) Tag Code). The definition for the next pages to be sent out for this message code include some user-defined code values. These ...
Page 154
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers process. If each page is successfully auto-negotiated (it matches the transmitted page), DTE Discovery completes as previously described. The five Next Pages consist of a message page and four user pages. ...
Page 155
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.12 Monitoring Operations 4.12.1 Monitoring Auto-Negotiation Auto-negotiation may be monitored as follows: • Bits 1.2 and 17. once the link is established. • Additional bits in Register 1 (refer ...
Page 156
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers When a long event (such as duplex status) occurs edge detected and starts the stretch timer. When the stretch timer expires, the edge detector is reset so that a ...
Page 157
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers The LXT9785/LXT9785E includes an IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible. 4.12.4 Boundary Scan Interface This interface consists of ...
Page 158
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.13 Cable Diagnostics Overview Debugging cable problems increases the overall cost of owning and operating a local area network. Cable Diagnostic tools were incorporated into the LXT9785 device to help customers ...
Page 159
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 4.13.3 Implementation Considerations Before performing Cable Diagnostics, the twisted-pair to be tested may be verified to be inactive. All applicable link configurations should be attempted. Cable Diagnostic tests may be started ...
Page 160
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 3. Poll Register bit 29.9. When this bit is set, the test is complete and Register bits 29.7:0 contain a value used to determine if a cable fault was found and ...
Page 161
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Link Hold-Off software control is enabled or disabled on individual ports by respectively setting or clearing Register bit 0.11, the power-down bit, during normal operation not required to have ...
Page 162
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 5.0 Application Information 5.1 Design Recommendations The LXT9785/LXT9785E is designed to comply with IEEE 802.3 requirements to provide outstanding receive Bit Error Rate (BER), and long-line-length performance. To achieve maximum performance ...
Page 163
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Intel recommends filtering the power supply to the analog VCC pins of the LXT9785/LXT9785E. This has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the ...
Page 164
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers • Place the magnetics as close as possible to the LXT9785/LXT9785E. • Keep transmit pair traces as short as possible; both traces should have the same length. • Avoid vias and ...
Page 165
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers • The transmit pair should contain a balance offset in the pull-up resistors to prevent PHY-to- fiber transceiver crosstalk amplification in power-down, loopback, and reset states (see fiber interface application note) ...
Page 166
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 5.3 Typical Application Circuits Figure 34 through Figure 37 on page 171 LXT9785E. Figure 38 on page 172 ® Figure 34. Intel LXT9785/LXT9785E Power and Ground Supply Connections GNDR/GNDT VCCR/VCCT LXT9785/9785E ...
Page 167
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 35. Intel LXT9785/LXT9785E Typical Twisted-Pair Interface LXT9785/9785E 1. The 100 Ω transmit load termination resistor typically required is integrated in the LXT9785/ LXT9785E. 2. The 100 Ω receive load ...
Page 168
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 36. Recommended Intel Circuitry +2.5V TPFONn TPFOPn LXT9785(E) SDn TPFINn TPFIPn SD_2P5V GNDPECL VCCPECL 1. Refer to the transceiver manufacturers’ recommendations for termination circuitry. 170 ® LXT9785/LXT9785E-to-3.3 V Fiber Transceiver ...
Page 169
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 37. Recommended Intel Circuitry TPFONn TPFOPn LXT9785(E) SDn TPFINn TPFIPn SD_2P5V GNDPECL VCCPECL 1. Refer to the transceiver manufacturers’ recommendations for termination circuitry. 2. See Figure 38 on page 172 ...
Page 170
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Figure 38. ON Semiconductor Triple PECL-to-LVPECL Translator 0.01 µF 5V 82Ω PECL Input Signal (5V Fiber Txcvr) 130Ω 172 5V 3.3V ON Semiconductor* Vcc Vcc ...
Page 171
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 6.0 Test Specifications Note: Table 51 through Table 81 the LXT9785/LXT9785E. These specifications are not guaranteed and are subject to change without notice. Minimum and maximum values listed in recommended operating ...
Page 172
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 52. Intel LXT9785/LXT9785E Operating Conditions (Sheet Parameter 100BASE-TX 100BASE-FX Operating 10BASE-T 3 Current - SMII Power-Down Auto-Negotiation 100BASE-TX 100BASE-FX Operating 10BASE-T Current - 3 SS-SMII Power-Down ...
Page 173
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 54. Intel LXT9785/LXT9785E Digital I/O DC Electrical Characteristics (VCCIO = 3.3 V +/- 5%) Parameter Input Low voltage Input High voltage Input current Output Low voltage Output Low voltage ...
Page 174
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 57. Intel LXT9785/LXT9785E 100BASE-TX Transceiver Characteristics Parameter Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot Jitter magnitude (measured differentially) 1. ...
Page 175
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 59. Intel LXT9785/LXT9785E 10BASE-T Transceiver Characteristics Parameter Peak differential output voltage Link transmit period Jitter magnitude added by the MAU and PLS sections Receive input impedance Link min receive ...
Page 176
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 39. Intel LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing REFCLK SYNC RxData TPFI ® Table 60. Intel LXT9785/LXT9785E SMII - 100BASE-TX Receive Timing Parameters Parameter RxData output delay from REFCLK ...
Page 177
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 40. Intel LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing REFCLK SYNC TxData TPFO ® Table 61. Intel LXT9785/LXT9785E SMII - 100BASE-TX Transmit Timing Parameters Parameter SYNC setup to REFCLK rising ...
Page 178
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 41. Intel LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing REFCLK SYNC RxData TPFI ® Table 62. Intel LXT9785/LXT9785E SMII - 100BASE-FX Receive Timing Parameters Parameter RxData output delay from REFCLK ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 42. Intel LXT9785/LXT9785E SMII - 100BASE-FX Transmit Timing REFCLK SYNC TxData TPFO ® Table 63. Intel LXT9785/LXT9785E SMII - 100BASE-FX Transmit Timing Parameters Parameter SYNC setup to REFCLK rising ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 43. Intel LXT9785/LXT9785E SMII - 10BASE-T Receive Timing REFCLK SYNC RxData TPFI ® Table 64. Intel LXT9785/LXT9785E SMII - 10BASE-T Receive Timing Parameters Parameter RxData output delay from REFCLK ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 44. Intel LXT9785/LXT9785E SMII - 10BASE-T Transmit Timing REFCLK SYNC TxData TPFO ® Table 65. Intel LXT9785/LXT9785E SMII-10BASE-T Transmit Timing Parameters Parameter SYNC setup to REFCLK rising edge and ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 45. Intel LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing REFCLK RxCLK RxSYNC RxData TPFI ® Table 66. Intel LXT9785/LXT9785E SS-SMII - 100BASE-TX Receive Timing Parameters Parameter REFCLK rising edge to ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 46. Intel LXT9785/LXT9785E SS-SMII - 100BASE-TX Transmit Timing TxCLK TxSYNC TxData TPFO ® Table 67. Intel LXT9785/LXT9785E SS-SMII - 100BASE-TX Transmit Timing Parameter TxSYNC setup to TxCLK rising edge ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 47. Intel LXT9785/LXT9785E SS-SMII - 100BASE-FX Receive Timing REFCLK RxCLK RxSYNC RxData TPFI ® Table 68. Intel LXT9785/LXT9785E SS-SMII - 100BASE-FX Receive Timing Parameters Parameter REFCLK rising edge to ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 48. Intel LXT9785/LXT9785E SS-SMII - 100BASE-FX Transmit Timing TxCLK TxSYNC TxData TPFO ® Table 69. Intel LXT9785/LXT9785E SS-SMII - 100BASE-FX Transmit Timing Parameters Parameter TxSYNC setup to TxCLK rising ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 49. Intel LXT9785/LXT9785E SS-SMII - 10BASE-T Receive Timing REFCLK RxCLK RxSYNC RxData TPFI ® Table 70. Intel LXT9785/LXT9785E SS-SMII - 10BASE-T Receive Timing Parameters Parameter REFCLK rising edge to ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 50. Intel LXT9785/LXT9785E SS-SMII - 10BASE-T Transmit Timing TxCLK TxSYNC TxData TPFO ® Table 71. Intel LXT9785/LXT9785E SS-SMII - 10BASE-T Transmit Timing Parameters Parameter TxSYNC setup to TxCLK rising ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 51. Intel LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing REFCLK RxData[1:0] TPFI CRS_DV ® Table 72. Intel LXT9785/LXT9785E RMII - 100BASE-TX Receive Timing Parameters Parameter RxData<1:0>, CRS_DV, RXER setup to ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 52. Intel LXT9785/LXT9785E RMII - 100BASE-TX Transmit Timing REFCLK TxData(1:0) TPFO TxEN ® Table 73. Intel LXT9785/LXT9785E RMII - 100BASE-TX Transmit Timing Parameters Parameter TxData<1:0>/TxEN setup to REFCLK rising ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 53. Intel LXT9785/LXT9785E RMII - 100BASE-FX Receive Timing REFCLK RxData[1:0] TPFI CRS_DV ® Table 74. Intel LXT9785/LXT9785E RMII - 100BASE-FX Receive Timing Parameters Parameter RxData<1:0>, CRS_DV, RXER setup to ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 54. Intel LXT9785/LXT9785E RMII - 100BASE-FX Transmit Timing REFCLK TxData(1:0) TPFO TxEN ® Table 75. Intel LXT9785/LXT9785E RMII - 100BASE-FX Transmit Timing Parameters Parameter TxData<1:0>/TxEN setup to REFCLK rising ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 55. Intel LXT9785/LXT9785E RMII - 10BASE-T Receive Timing REFCLK RxData[1:0] TPFI CRS_DV ® Table 76. Intel LXT9785/LXT9785E RMII - 10BASE-T Receive Timing Parameters Parameter RxData<1:0>, CRS_DV setup to REFCLK ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 56. Intel LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing REFCLK TxData(1:0) TPFO TxEN ® Table 77. Intel LXT9785/LXT9785E RMII - 10BASE-T Transmit Timing Parameters Parameter TxData<1:0>/TxEN setup to REFCLK rising ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 57. Intel LXT9785/LXT9785E Auto-Negotiation and Fast Link Pulse Timing Clock Pulse TPFOP ® Figure 58. Intel LXT9785/LXT9785E Fast Link Pulse Timing TPFOP ® Table 78. Intel LXT9785/LXT9785E Auto-Negotiation and ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 59. Intel LXT9785/LXT9785E MDIO Write Timing (MDIO Sourced by MAC) MDC MDIO ® Figure 60. Intel LXT9785/LXT9785E MDIO Read Timing (MDIO Sourced by PHY) MDC MDIO ® Table 79. ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Figure 61. Intel LXT9785/LXT9785E Power-Up Timing ® Table 80. Intel LXT9785/LXT9785E Power-Up Timing Parameters Parameter Voltage Threshold Power-up recovery time 2 Software power-down 1. Typical values are at 25° C ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers 7.0 Register Definitions The LXT9785/LXT9785E register set includes multiple 16-bit registers, 18 registers per port. Table 82 presents a complete register listing. through Table 100, “Cable Diagnostics Register (Address 29, Hex ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers ® Table 82. Intel LXT9785/LXT9785E Register Set (Sheet Address Register Name 27 “Trim Enable Register (Address 27, Hex 1B)” 28 Reserved 29 “Cable Diagnostics Register (Address 29, Hex ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 83. Control Register (Address 0) (Sheet Bit Name 7 Collision Test Speed Selection 6 1000 Mbps 5:0 Reserved 1. R/W = Read/Write Self Clearing when ...
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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Table 84. Status Register (Address 1) Bit Name Auto-Negotiation 5 complete 4 Remote Fault Auto-Negotiation 3 Ability 2 Link Status 1 Jabber Detect 0 Extended Capability Read Only ...